Scheduling program instruction execution by using fence instructions
AssigneeNVIDIA Corporation
InventorsChristian Rouet, Rui M. Bastos, Emmett M. Kilgariff
Life of this patent
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Abstract
A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.
Claims15
A method of controlling the scheduling of program instruction execution, comprising:
- determining that a first program instruction within a sequence of program instructions should be explicitly scheduled for execution by a first processing unit residing within a processing pipeline;
- generating a very large instruction word (VLIW) that includes a first slot corresponding to the first processing unit;
- inserting a fence instruction into the sequence of program instructions immediately before and separate from the first program instruction to produce a modified sequence of program instructions;
- executing the fence instruction within the modified sequence of program instructions and, in response, inserting the first program instruction into the first slot within the VLIW specified by the first fence instruction, wherein the first slot corresponds to the first processing unit;
- and
- dispatching the VLIW into the processing pipeline for execution.
A system for scheduling execution of program instructions, comprising:
- a first processing unit residing within a processing pipeline configured to execute a first program instruction and forward source operands to a second processing unit residing within the processing pipeline;
- the second processing unit configured to execute a second program instruction;
- and
- an instruction scheduling unit configured to:
- generate a very large instruction word (VLIW) that includes a first slot corresponding to the first processing unit and a second slot corresponding to the second processing unit,
- execute a first fence instruction and, in response, insert the first program instruction into the first slot, wherein the first program instruction immediately follows the first fence instruction, and the first fence instruction specifies the first slot within the VLIW,
- execute a second fence instruction and, in response, insert a second program instruction into the second slot, wherein the second program instruction immediately follows the second fence instruction, and the second fence instruction specifies the second slot within the VLIW, and
- dispatch the VLIW into the processing pipeline for execution.
A method of executing a sequence of program instructions including a fence instruction specifying a scheduling constraint for a first program instruction, the method comprising:
- generating a very large instruction word (VLIW) that includes a first slot corresponding to a first processing unit residing within a processing pipeline;
- determining whether the first processing unit in the processing pipeline is available to execute the first program instruction;
- scheduling the first program instruction for execution by the first processing unit if the first processing unit is available to execute the first program instruction in a first pass through the processing pipeline by executing the fence instruction and, in response, inserting the first program instruction into the first slot within the VLIW, wherein the first fence instruction specifies the first slot, or scheduling the first program instruction for execution by the first processing unit during a second pass through the processing pipeline, if the first processing unit is not available to execute the first program instruction in a first pass, by executing the fence instruction and, in response, inserting the first program instruction into the first slot within another VLIW, wherein the first program instruction immediately follows the fence instruction;
- and
- dispatching either the VLIW or the another VLIW into the processing pipeline for execution.
Dependencies are inferred from the claim text.