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US 7,624,250 B2Granted
Heterogeneous multi-core processor having dedicated connections between processor cores
AssigneeIntel Corporation
InventorsSinn Wee Lau, Choon Yee Loh, Kar Meng Chan
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Abstract
The disclosure describes a processor having processor cores integrated on the same die that have different functional operationality. The processor also includes a chain of multiple dedicated unidirectional connections spanning processor cores. The multiple dedicated unidirectional connections terminate in registers within the respective processor cores. The registers may form a queue such as a ring queue.
Claims22
A processor, comprising:
- multiple cores integrated on a single semiconductor die, the multiple cores including:
- a first set of processor cores integrated on the single semiconductor die having the same functional operationality;
- and
- a second set of at least one processor core integrated on the single semiconductor die having a different functional operationality than a processor core of the first set of processor cores;
- a chain of multiple dedicated unidirectional connections spanning the first and second set of processor cores, at least one of the multiple dedicated unidirectional connections being between a one of the first set of processor cores and a one of the second set of processor cores, the multiple dedicated unidirectional connections terminating in registers within the respective processor cores;
- wherein the registers in a one of the second set of processor cores comprises multiple registers that a one of the first set of processor cores accesses as a circular ring queue;
- wherein the second set of processor cores includes at least one ring register;
- and
- wherein the ring register is undated when an operation is performed on the circular ring.
6 more elements
A network device, comprising:
- multiple blades;
- a switch fabric interconnecting the multiple blades;
- wherein at least one of the multiple blades comprises a blade having a processor having multiple cores integrated on a single semiconductor die, the multiple cores including:
- a first set of processor cores integrated on the single semiconductor die having the same functional operationality, the first set of processor cores each having multiple hardware contexts for multiple, respective, threads of execution;
- and
- a second set of at least one processor core integrated on the single semiconductor die having a different functional operationality than a processor core of the first set of processor cores;
- a chain of multiple dedicated unidirectional connections spanning the first and second set of processor cores, at least one of the multiple dedicated unidirectional connections being between a one of the first set of processor cores and a one of the second set of processor cores, the multiple dedicated unidirectional connections terminating in registers within the respective processor cores;
- wherein the registers in a one of the second set of processor cores comprises multiple registers that a one of the first set of processor cores accesses as a circular ring queue;
- wherein the second set of processor cores includes at least one ring register;
- and
- wherein the ring register is updated when an operation is performed on the circular ring.
8 more elements
A method, comprising:
- at a processor having multiple cores integrated on a single semiconductor die, the multiple cores including:
- a first set of processor cores integrated on the single semiconductor die having the same functional operationality;
- and
- a second set of at least one processor core integrated on the single semiconductor die having a different functional operationality than a processor core of the first set of processor cores;
- a chain of multiple dedicated unidirectional connections spanning the first and second set of processor cores, at least one of the multiple dedicated unidirectional connections being between a one of the first set of processor cores and a one of the second set of processor cores, the multiple dedicated unidirectional connections terminating in registers within the respective processor cores, wherein the registers terminating a unidirectional connection within a respective processor core form a queue;
- and
- transferring a first set of data from a one of the first set of processor cores to a one of the second set of processor cores via a one of the multiple dedicated unidirectional connections.
4 more elements
Dependencies are inferred from the claim text.