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US 7,624,249 B2Granted
Processor multi-partition security architecture
OwnerDennis O'Connorinventor
Life of this patent
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Abstract
A state machine may be coupled to a memory management unit configuration table (MMUCT) stored in a memory to index an entry from the MMUCT. A parameter associated with the entry may be used to control operations associated with a memory management unit (MMU). The MMU may be used to control access to a set of page tables stored in the memory. Other embodiments may be described and claimed.
Claims9
An apparatus, including:
- a state machine within a processor, the state machine coupled to a memory management unit configuration table (MMUCT) stored in a memory, the state machine to index an entry from the MMUCT and to load the entry into at least one memory management unit (MMU) control register;
- and
- an MMU configuration table base pointer register (MCTBR) coupled to the state machine to provide a base address to locate the MMUCT within the memory.
A system, including:
- a state machine within a processor, the state machine coupled to a memory management unit configuration table (MMUCT) stored in a memory, the state machine to index an entry from the MMUCT and to load the entry into at least one memory management unit (MMU) control register;
- an MMU configuration table base pointer register (MCTBR) coupled to the state machine to provide a base address to locate the MMUCT within the memory;
- a process identification register (PID) coupled to the state machine to notify the state machine that the PID has been modified and to supply an index value to be used by the state machine to index the entry from the MMUCT;
- and
- a flash memory coupled to the processor.
2 more elements
A method, including:
- locating a memory management unit configuration table (MMUCT) stored in a memory using a base address contained in an MMU configuration table base pointer register (MCTBR) coupled to a state machine;
- indexing an entry from the MMUCT using the state machine;
- and
- controlling access to a set of page tables stored in the memory using a memory management unit (MMU), wherein the MMU operates according to at least one parameter associated with the entry indexed from the MMUCT.
1 more element
An apparatus, including:
- a state machine within a processor, the state machine coupled to a memory management unit configuration table (MMUCT) stored in a memory, the state machine to index an entry from the MMUCT and to load the entry into at least one memory management unit (MMU) control register;
- and
- a process identification register (PID) coupled to the state machine to notify the state machine that the PID has been modified and to supply an index value to be used by the state machine to index the entry from the MMUCT.
Dependencies are inferred from the claim text.