Memory controller and data processing system

A semiconductor device comprising:

• a memory controller controlling a memory which has a plurality of word lines, bit lines, and memory cells, operating in a first mode or a second mode, and including a counter counting a number of successive accesses to different word lines,
• wherein during the first mode, the memory controller controls the memory to pre-charge the plurality of bit lines after a read access,
• wherein during the second mode, the memory controller outputs signals for next read access without pre-charging the plurality of bit lines after a read access, and
• wherein the memory controller changes from the second mode to the first mode after different word lines are accessed a predetermined number of times successively, a number of the predetermined times being able to be set in the counter,
• wherein the memory controller further comprises, a page access decision circuit, a mode changing circuit, and an address generating circuit,
• wherein the word lines are selected by row address, and
• wherein the page decision circuit compares a row address inputted to the memory controller and the previous row address,
• wherein the mode changing circuit receives signals from the page decision circuit and counts the number of successive accesses to different word lines by the counter, and
• wherein the address generating circuit receives signals from, the page decision circuit and from the mode changing circuit and outputs a command and an address to the memory.