Method of and circuit for enabling variable latency data transfers

A method of enabling variable latency data transfers in an integrated circuit having a plurality of peripheral devices transmitting data within said integrated circuit, said method comprising the steps of:

• coupling a memory controller between a processor of said integrated circuit having a programmable resource and a peripheral device, said memory controller controlling the transfer of data to and from said processor;
• implementing a first function in said programmable resource of said peripheral device;
• receiving a first address for a first data transfer between said processor and said peripheral device by way of said memory controller;
• transferring data for said first data transfer during a single clock cycle of said peripheral device after a first latency period which is unknown to said processor, said first latency period comprising a first number of clock cycles of a clock driving said peripheral device, wherein said first number of clock cycles is determined by said first function implemented by said peripheral device;
• generating, by said peripheral device, a first data transfer complete signal associated with the completion of the step of transferring said data for said first data transfer after said first latency period, wherein said first data transfer complete signal defines said first latency period, wherein said data for said first data transfer is available at said memory controller during a read and at said peripheral device during a write during the same clock cycle that said first data transfer complete signal is received by said memory controller;
• receiving a second address for a second data transfer between said memory controller and said peripheral device;
• transferring data for said second data transfer during a single clock cycle of said peripheral device after a second latency period comprising a second number of clock cycles of said clock driving said peripheral device, wherein said second number of clock cycles is different than said first number of clock cycles;
• generating, by said peripheral device, a second data transfer complete signal associated with the completion of the step of transferring said data for said second data transfer after said second latency period, wherein said second data transfer complete signal defines said second latency period;
• and
• receiving said second data transfer complete signal at said memory controller from said peripheral device based upon a requirement of said first function implemented in said peripheral device, wherein said data for said second data transfer is available at said memory controller during a read and at said peripheral device during a write during the same clock cycle that said second data transfer complete signal is received by said memory controller.

A method of enabling variable latency data transfers in an integrated circuit having a plurality of peripheral devices transmitting data within said integrated circuit, said method comprising the steps of:

• providing a processor of said integrated circuit communicating with said plurality of peripheral devices of said integrated circuit, said processor operating at a first frequency according to a first clock signal;
• coupling a memory controller of said integrated circuit to said processor, said memory controller controlling the transfer of data to and from said processor;
• enabling communication by way of programmable interconnect elements with a memory implemented as a peripheral device which is operated at a second frequency according to a second clock signal;
• coupling an address from said memory controller to said memory;
• receiving a read address valid signal at said memory from said memory controller;
• reading data from said memory during a single clock cycle of said peripheral device after a variable latency period which is unknown to said processor, said variable latency period comprising a number of clock cycles of said second clock signal;
• generating, by said peripheral device, a read complete signal associated with the completion of the step of reading said data from said memory after said variable latency period, wherein said read complete signal defines said variable latency period;
• and
• receiving a read complete signal at said memory controller from said memory after said variable latency period, wherein said data read from said memory is available at said memory controller during the same clock cycle that said read complete signal is received by said memory controller.

A method of enabling variable latency data transfers in an integrated circuit having a plurality of peripheral devices transmitting data within said integrated circuit, said method comprising the steps of:

• providing a processor of said integrated circuit communicating with said plurality of peripheral devices, said processor operating at a first frequency according to a first clock signal;
• coupling a memory controller of said integrated circuit to said processor, said memory controller controlling the transfer of data to and from said processor;
• enabling communication by way of programmable interconnect elements with a memory implemented as a peripheral device which is operated at a second frequency according to a second clock signal;
• receiving a write address at said memory from said memory controller;
• receiving an address valid signal at said memory from said memory controller;
• storing said write address to said memory;
• writing data from said processor to said write address during a single clock cycle of said peripheral device;
• generating, by said peripheral device, a write complete signal associated with the completion of the step of writing data from said processor to said write address, wherein said write complete signal defines a variable latency period for writing said data;
• and
• receiving said write complete signal at said memory controller from said memory after said variable latency period which is unknown to said processor, said variable latency period comprising a number of clock cycles of a clock driving said memory, wherein said data written to said memory is available at said memory during the same clock cycle that said write complete signal is received by said memory controller.

An integrated circuit enabling a variable latency data transfer, said integrated circuit comprising:

• a processor;
• a peripheral device implementing a function in a configurable logic resource coupled to receive data from and provide data to said processor;
• a memory controller coupled between said processor and said peripheral device, said memory controller enabling a variable latency data transfer during a single clock cycle of said peripheral device by transferring data of an address after a variable latency period which is unknown to said processor, said variable latency period comprising a number of clock cycles of a clock driving said peripheral device based upon a requirement of said function implemented in said peripheral device;
• an address valid signal coupled from said memory controller to said peripheral device;
• and
• a transfer complete signal generated by said peripheral device and coupled from said peripheral device to said memory controller after said variable latency period based upon said requirement of said function implemented in said configurable resource of said peripheral device, wherein said transfer complete signal is associated with the completion of transferring data between said processor and said peripheral device by way of said memory controller and defines said variable latency period, wherein said data transferred between said processor and said peripheral device is available at said memory controller during a read and at said peripheral device during a write during the same clock cycle that said transfer complete signal is received by said memory controller.

An integrated circuit enabling a variable latency data transfer, said integrated circuit comprising:

• a processor;
• an address select circuit of a memory controller coupled to said processor, said address select circuit comprising a multiplexer for selecting an address location received from said processor;
• an address hold circuit of said memory controller coupled to the output of said address select circuit, said address hold circuit comprising a register for holding a selected address during a variable latency period until a data transfer complete signal is received, wherein said variable latency period is unknown to said processor;
• and
• a peripheral device coupled to said processor by way of said memory controller for transferring data of said selected address between said processor and said peripheral device after said variable latency period comprising a number of clock cycles of a clock driving said peripheral device during a single clock cycle of said peripheral device, said peripheral device being implemented in a configurable resource and coupled to said address hold circuit of said memory controller, said peripheral device outputting said data transfer complete signal based upon a requirement of a function implemented in said configurable resource of said peripheral device, wherein said data transfer complete signal is associated with the completion of transferring said data of said selected address between said processor and said peripheral device and defines said variable latency period, wherein said data transferred between said processor and said peripheral device is available at said memory controller during a read and at said peripheral device during a write during the same clock cycle that said data transfer complete signal is received by said memory controller.

An integrated circuit enabling a variable latency data transfer, said integrated circuit comprising:

• a processor;
• a memory controller coupled to said processor;
• a peripheral device implementing a function in a configurable logic resource and coupled to receive a read address from said processor by way of said memory controller;
• an output coupled to said peripheral device, said output providing data associated with said read address from said peripheral device after a variable latency period comprising a number of clock cycles of a clock driving said peripheral device during a single clock cycle of said peripheral device, wherein said variable latency period is unknown to said processor;
• and
• a data hold circuit coupled to said output, said data hold circuit comprising a register for holding said data associated with said read address to be transferred to said processor until a data transfer complete signal is received after said variable latency period based upon a requirement of said function implemented in said configurable resource of said peripheral device, wherein said data transfer complete signal is associated with the completion of transferring said data associated with said read address from said peripheral device and defines said variable latency period, wherein said data transferred from said peripheral device is available at said memory controller during the same clock cycle that said data transfer complete signal is received by said memory controller.

An integrated circuit enabling a variable latency data transfer, said integrated circuit comprising:

• processor means;
• configurable resource means for implementing a function;
• address select means of a memory controller coupled to said processor means, said address select means selecting an address location received from said processor means;
• address hold means of said memory controller coupled to the output of said address select means, said address hold means holding a selected address during a variable latency period comprising a number of clock cycles of a clock driving said configurable resource means until a data transfer complete signal is received based upon a requirement of said function implemented in said configurable resource means, wherein said variable latency period is unknown to said processor means;
• memory means coupled to said address hold means, said memory means outputting data after said variable latency period during a single clock cycle of said configurable resource means, wherein said data transfer complete signal is associated with the completion of outputting said data after said variable latency period and defines said variable latency period and said data transferred between said processor means and said configurable resource means is available at said memory controller during the same clock cycle that said data transfer complete signal is received by said memory controller;
• and
• data hold means of said memory controller coupled to an output of said memory means, said data hold means holding said data to be transferred to said processor means after said variable latency period.