Clock extracting method and apparatus thereof
AssigneeFujitsu Limited
InventorsFumio Futami, Shigeki Watanabe
Life of this patent
Estimating the term…
Abstract
A clock extracting apparatus arranges bit intervals of a signal light train incident on a signal light processing section to have uneven periods, makes bit intervals between a predetermined signal light and signal lights adjacent to the predetermined signal light to be longer than a switching time of an electro-optical gate, selectively demultiplexes the predetermined signal light using the electro-optical gate, and extracts a clock synchronized with the signal light train from the demultiplexed signal light. Thus, it becomes possible to extract a clock synchronized with an ultra-high speed from a signal light train.
Claims15
A clock extracting method of extracting a clock synchronized with a signal light train, comprising:
- a signal light processing step performed using an optical switch, of arranging bit intervals of said signal light train having the bit intervals shorter than a switching time of said optical switch, at uneven periods, to make a first bit interval between a predetermined signal light and a first adjacent signal light before said predetermined signal light and a second bit interval between said predetermined signal light and a second adjacent signal light following said predetermined signal light to be longer than the switching time of said optical switch;
- an optical switch processing step of selectively demultiplexing said predetermined signal light from said signal light train processed by said signal light processing step using said optical switch, to generate a signal light at a bit rate lower than that of said signal light train;
- and
- an electric clock extracting step of electrically extracting a clock synchronized with said signal light train from the signal light converted into an electrical signal by a photoelectric converter.
A clock extracting apparatus for demultiplexing a signal light train using an optical switch to generate a signal light at a bit rate lower than that of said signal light train, and electrically extracting, from said signal light, a clock synchronized with said signal light train, comprising:
- a signal light processing section that, for said signal light train having bit intervals shorter than a switching time of said optical switch, arranges said bit intervals at uneven periods, to make a first bit interval between a predetermined signal light and a first adjacent signal light before said predetermined signal light and a second bit interval between said predetermined signal light and a second adjacent signal light following said predetermined signal light to be longer than the switching time of said optical switch;
- an optical switch processing section that selectively demultiplexes said predetermined signal light from said signal light train processed by said signal light processing section using said optical switch, to generate a signal light at a bit rate lower than that of said signal light train;
- and
- an electric clock extracting section that electrically extracts a clock synchronized with said signal light train from the signal light generated by said optical switch processing section.
Dependencies are inferred from the claim text.