System and method for effectuating the transfer of data blocks including a header block across a clock boundary

A method for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain, wherein said first clock domain is configured to operate with a first clock signal (CLK1) and said second clock domain is configured to operate with a second clock signal (CLK2), comprising:

• processing a header block associated with data blocks that are to be sent from said first clock domain to said second clock domain via a synchronizer;
• generating a hint signal that gives advance notification of a possible data transfer operation responsive to said header block and positioning said hint signal at least one cycle prior to the location of said data blocks, said processing said header block and said generating said hint signal being performed in said first clock domain;
• transmitting said hint signal to a control block in said second clock domain, thereby indicating that said data blocks may be sent to receive circuitry in said second clock domain;
• and
• generating appropriate control signals based on said hint signal for controlling output of said data blocks in a particular ordered grouping.

A computer system having circuitry for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain, wherein said first clock domain is configured to operate with a first clock signal (CLK1) and said second clock domain is configured to operate with a second clock signal (CLK2), said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, wherein N/M>1, comprising:

• means for processing a header block associated with said data blocks to determine whether said data blocks may be sent from said first clock domain to said second clock domain via a synchronizer;
• means for generating a hint signal that gives advance notification of a possible data transfer operation responsive to said header block wherein said hint signal is configured to be positioned at least one cycle prior to the possible location of said data blocks, said means for processing a header block and said means for generating a hint signal being disposed in said first clock domain;
• and
• means for transmitting said hint signal to a control block in said second clock domain, thereby indicating that said data blocks may be sent to receive circuitry in said second clock domain, wherein said control block generates appropriate control signals based on said hint signal for controlling output of said data blocks in a particular ordered grouping.