Semiconductor memory device comprising data path controller and related method

A semiconductor memory device outputting data in accordance with each of a first edge and a second edge of a system clock signal, the device comprising a system clock generating the system clock signal, a first control clock signal, and a second control clock signal;

• a data sensing output unit respectively providing first and second data to first and second data paths, wherein the first and second data are sensed from selected memory cells;
• a data output circuit serially outputting the first and second data at a single data Input/Output (I/O) pad;
• a data transmitter operationally connecting the first data path to the data output circuit through only a single first transmission gate responsive to the first control clock signal, and operationally connecting the second data path to the data output circuit through only a single second transmission gate responsive to the second control clock signal;
• and
• a data path controller connected between the data sensing output unit and the data transmitter, and delaying the first data on the first data path by a first delay period using a first delay element and delaying the second data on the second data path by a second delay period different from the first delay period using a second delay element, wherein the second delay element comprises a series connected bit conversion encoder and decoder disposed along the second data path.

A method for outputting data from a double data rate (DDR) semiconductor memory device, the method comprising:

• sensing, amplifying and outputting first data via a first data path and second data via a second data path parallel to the first data path;
• before passing the first and second data to a data transmitter, delaying the first data on the first data path by a first delay period using a first delay element and delaying the second data on the second data path by a second delay period different from the first delay period using a second delay element, wherein the first delay element is a first driver disposed along the first data path line, the second delay element is a second driver disposed along the second data path line, and the second driver is smaller than the first driver;
• passing the first and second data through the data transmitter via parallel signal paths, wherein passing the first data through the data transmitter is controlled by a single first transmission gate responsive to a first control clock signal and passing the second data through the data transmitter is controlled by a single second transmission gate responsive to a second control clock signal different from the first control clock signal;
• and
• converting the first and second data passed from the data transmitter into serial first and second data, and outputting the serial first and second data at a single Input/Output (I/O) pad.