US 7,623,405 B2 · SRAM with switchable power supply sets of voltages

Abstract

A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

Claims25

Dependent claims

A circuit, comprising:

a memory cell having a high voltage supply node and a low voltage supply node;
first power supply multiplexing circuitry having a first input for receiving a first high supply voltage and a second input for receiving a second high supply voltage that is less than the first high supply voltage, the first power supply multiplexing circuitry being responsive to a first control signal, wherein the first power supply multiplexing circuitry applies the first high supply voltage to the high voltage supply node if the first control signal has a first state, and applies the second high supply voltage to the high voltage supply node if the first control signal has a second state;
second power supply multiplexing circuitry having a first input for receiving a first low supply voltage and a second input for receiving a second low supply voltage that is greater than the first low supply voltage, the second power supply multiplexing circuitry being responsive to a second control signal, wherein the second power supply multiplexing circuitry applies the first low supply voltage to the low voltage supply node if the second control signal has a first state, and applies the second low supply voltage to the low voltage supply node if the second control signal has a second state.

A circuit, comprising:

an array of memory cells, the array being divided into a plurality of memory blocks, each memory block having a high voltage supply node and a low voltage supply node for the cells within the memory block;
an address decoder circuit which decodes an address in the array, the address decoder circuit generating a mode control signal for each memory block in the array, the mode control signal having an active read or write mode state when cells in the memory block are being addressed and the mode control signal having a standby no-read or no-write state when cells in the memory block are not being addressed;
circuitry associated with each memory block and which operates responsive to one of the mode control signals to selectively apply a first set of voltages to the high and low voltage supply nodes of the memory block if the mode control signal is in the active read or write mode state and apply a second set of voltages to the high and low voltage supply nodes of the memory block if the mode control signal is in the standby no-read or no-write state.

Dependencies are inferred from the claim text.

SRAM with switchable power supply sets of voltages

Life of this patent

SRAM with switchable power supply sets of voltages

Life of this patent

Abstract

Claims25