Memory device having concurrent write and read cycles and method thereof

A memory device comprising:

• a first latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal;
• a bit cell comprising a storage component;
• a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase;
• and
• a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.

A memory device comprising:

• a first latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the bit value for a first phase and a second phase of a cycle of the clock signal, wherein the second phase follows the first phase;
• a second latch having an input configured to receive a write enable signal, an input to receive the clock signal, and an output to provide a latched write enable signal for the first phase and the second phase;
• a write row driver having an input to receive the latched write enable signal, the write row driver configured to assert a write word line in response to the latched write enable signal having a first state and to deassert the write word line in response to the latched write enable signal having a second state;
• a read row driver having an input to receive a read enable signal, the read row driver configured to assert a read word line in response to the read enable signal having a first state and to deassert the read word line in response to the read enable signal having a second state;
• and
• a bit cell array comprising a bit cell configured to selectively enable write access to the bit cell based on a state of the write word line and selectively enable read access to the bit cell based on a state of the read word line.