Semiconductor memory device operating a self refreshing and an auto refreshing

#This application is based upon and claims the benefit of priority from Japanese patent application No. 2006-351296, the disclosure of which is incorporated herein in its entirety by reference.

#1. Field of the Invention

#The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a dynamic memory cell requiring a refresh operation in order to retain data therein.

#FIG. 1 is a circuit block diagram showing the configuration of a section for generating an RASB signal in a semiconductor memory device according to a first embodiment of the present invention;

#FIG. 2 is a timing chart showing a timing chart showing a waveform of each part of the RASB control circuit shown in FIG. 1 during the self refreshing;

#FIG. 3 is a circuit diagram showing the circuit configuration of the oscillator;

#Now, exemplary embodiments of the present invention will be described with reference to accompanying drawings, wherein similar constituent elements are designated by similar reference numerals throughout the drawings.

#FIG. 1 shows the circuit configuration of a section for generating an RASB signal in a semiconductor memory device according to a first embodiment of the present invention. As the refresh operation executed in the semiconductor memory device, auto refreshing (first refreshing) and self refreshing (second refreshing) are considered. An RASB control circuit 100 includes a command decoder 101, an oscillator 102, ROM circuits 103 and 104, OR gates 105 and 110, an n-bit counter 106, a programmable decoder 107, NOR gates 108, 111, and 112, and an AND gate 109. The command decoder 101 decodes a command input from an external terminal, such as RAS or CAS terminal, and generates an RF_cmd signal for executing the refresh operation during the auto refreshing.

#The oscillator 102 starts oscillating operation based on SR_EN signal, and oscillates at a predetermined oscillating period. This oscillating period of the oscillator 102 can be adjusted by CODEi signal having a predetermined number of bits output from the ROM circuit 103. The ROM circuit 103 is configured by a FUSE circuit, for example. The ROM circuit 103 has a number of fuses corresponding to the number of bits of the output CODEi signal, and each of the fuses is arranged between the power source line and the output node. During the fuse-cutting, a fuse corresponding to a bit “0” is cut, and a fuse corresponding to a bit “1” is left uncut. On the reference side, each bit is determined by existence or nonexistence of a voltage, to read out the CODEi signal.