Semiconductor device including multi-bit memory cells and a temperature budget sensor
AssigneeQimonda North America Corp.
InventorsJan Boris Philipp, Thomas Happ
Life of this patent
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Abstract
One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result. The circuit refreshes the plurality of multi-bit memory cells based on the first comparison result.
Claims35
A semiconductor device, comprising:
- a plurality of multi-bit memory cells, wherein each of the plurality of multi-bit memory cells is programmable into each of more than two states;
- a first temperature budget sensor;
- and
- a circuit that compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result, and refreshes the plurality of multi-bit memory cells based on the first comparison result, wherein the first temperature budget sensor includes a multi-bit memory cell that is programmable into each of more than two states and the first temperature budget sensor is written to one of the more than two states.
A memory comprising:
- an array of multi-bit phase change memory cells, wherein each of the multi-bit phase change memory cells includes phase change material programmable into each state of multiple non-crystalline states;
- a first temperature budget sensor including the phase change material programmable into each state of the multiple non-crystalline states;
- and
- a circuit that compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result and refreshes the array of multi-bit phase change memory cells based on the first comparison result.
A semiconductor device, comprising:
- a plurality of multi-bit memory cells, wherein each of the plurality of multi-bit memory cells is programmable into each of more than two states;
- a first temperature budget sensor that includes a first multi-bit memory cell that is programmable into each of the more than two states;
- and
- a circuit, wherein the first temperature budget sensor is written to one of the more than two states and the circuit compares a first signal from the first temperature budget sensor to a first resistivity band to obtain a first result, and refreshes the plurality of multi-bit memory cells based on the first result.
A memory comprising:
- an array of multi-bit phase change memory cells, wherein each of the multi-bit phase change memory cells is programmable into each of more than two states;
- means for monitoring a temperature budget of the array of multi-bit phase change memory cells;
- and
- means for refreshing the array of multi-bit phase change memory cells in response to the temperature budget exceeding a threshold value.
A method of operating a memory, comprising:
- monitoring a temperature budget of an array of multi-bit phase change memory cells that are programmable into each of more than two states;
- and
- refreshing the array of multi-bit phase change memory cells in response to the temperature budget exceeding a threshold value.
A method of operating a memory, comprising:
- writing a first multi-bit phase change memory cell to substantially a lower resistance end of a first state of more than two states;
- sensing a first signal from the first multi-bit phase change memory cell;
- comparing the first signal to a first reference signal to obtain a first comparison result;
- and
- refreshing an array of multi-bit phase change memory cells based on the first comparison result.
Dependencies are inferred from the claim text.