Semiconductor memory device and semiconductor device

#The present application is claiming the priority of the earlier Japanese patent application No. 2006-240474 filed on Sep. 5, 2006, the entire disclosure thereof being incorporated herein by reference thereto.

#The present invention relates to a semiconductor device. More specifically, the invention relates to a clock-synchronized type semiconductor memory device.

#In recent years, DLL (Delay Lock Loop) circuits have been in wide spread use for delay-synchronization in semiconductor devices such as clock-synchronized type semiconductor memory devices. In modules, current consumption of DLLs corresponding to the number of semiconductor memory devices with DLLs mounted thereon are further required. This has become a factor that increases power consumption as a system.

#FIG. 1 is a diagram showing a bonding state when two of chips are stacked in a first example of the present invention;

#FIG. 2 is a diagram showing connection configurations between each of semiconductor memory devices and dedicated pads in the first example of the present invention;

#FIG. 3 is a diagram showing a configuration of a DLL circuit in the first example of the present invention and a connecting relationship between the DLL circuit and each of the dedicated pads;

#In order to describe the present invention described above in further detail, a description will be given below with reference to appended drawings. In a stacked module wherein semiconductor memory devices with DLL (Delay Lock Loop) circuits are stacked, or in a multi-chip module (MCM) having the semiconductor memory devices with DLL circuits, there is provided a dedicated pad (PAD) for sharing a clock signal (CLK) having delay adjusted by a DLL between one of the semiconductor memory devices and other semiconductor memory device. The DLL in the one semiconductor memory device is operated, while the DLL in the other semiconductor memory device is not operated. A flying lock clock signal which is delay-synchronized with an external clock signal (such as a differential clock CLK, CLKB) and generated from a clock signal delay adjusted by the DLL is output from the dedicated pad of the one semiconductor memory device. The other semiconductor memory device receives the flying lock clock signal from the dedicated pad. Most of DLL circuits on chips to which the flying lock clock signals are supplied from a chip where the DLL circuit is operating do not operate. Thus, current consumptions of the DLL circuits can be reduced. As a result, current consumption of the entire module can be reduced. A description will be given below in connection with examples.

#FIGS. 1 and 2 are diagrams showing a configuration of an example of the present invention. FIG. 1 shows a bonding state when two chips of semiconductor memory devices each including dedicated pads for a DLL are stacked. FIG. 2 is a diagram for explaining an internal configuration and an operation of a semiconductor memory device including a dedicated pad (DPIO) for transferring a flying lock clock signal generated from a locked clock signal of the DLL and delay-synchronized with an external differential clock signal (CLK, CLKB).

#Referring to FIG. 2, a chip C1 and a chip C2 are provided in a stacked module. The chip C1 is set so that a flying lock clock (LIOCLK) is supplied to other chip via the dedicated pad (dedicated PAD) by initial setting in accordance with an external command such as a mode register set command or using a signal from a bonding option pad (PAD) provided separately. The chip C2 is set so that the flying lock clock (LIOCLK) is captured from outside.