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US 7,623,396 B2Granted
Method and apparatus for power reduction on a processor bus
AssigneeIntel Corporation
InventorsChunyu Zhang, Chris D. Matthews
Life of this patent
Estimating the term…
Abstract
Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.
Claims18
An apparatus comprising:
- address signal logic, the address signal logic to operate in a power savings mode by driving an address signal for a quarter of a clock period and to transmit a logical 1 while the address signal is not driven;
- and
- address strobe logic, the address strobe logic to operate in the power savings mode by aligning an edge of an address strobe with a valid address signal.
A method comprising:
- upon detecting a power savings mode, driving an address signal on an address line for a quarter of a clock period;
- transmitting a logical 1 on the address line while the address signal is not driven;
- and
- aligning an edge of an address strobe with the address signal while the address signal is valid.
1 more element
Dependencies are inferred from the claim text.