US 7,623,394 B2Granted

High voltage generating device of semiconductor device

AssigneeHynix Semiconductor Inc.

InventorYoung Su Kang

Life of this patent

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Abstract

A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and performs a pumping operation in response to the first enable signal and a first clock signal to generate the first high voltage. The second high voltage pimp unit compares a second high voltage and a second reference voltage to generate a second enable signal, and perform a pimping operation in response to the second enable signal and a second clock signal to generate the second high voltage. The clock signal generating unit generates the first clock signal or the second clock signal in response to the first enable signal and the second enable signal when at least one of the first enable signal and the second enable signal is enabled.

Claims1

Dependent claims

A high voltage generator of a semiconductor device, comprising:

a first high voltage pump unit to generate a first high voltage in response to a first clock signal generated according to an oscillator enable signal output from a clock encoder;
a second high voltage pump unit to generate a second high voltage in response to a second clock signal generated according to the oscillator enable signal;
and
a clock generating unit to compare an output voltage of the first high voltage pump unit and a reference voltage, and compare a first enable signal according to the comparison result, an output voltage of the second high voltage pump unit, and the reference voltage, and generate the first clock signal and the second clock signal in response to a second enable signal according to the comparison result,
wherein the clock generating unit comprises the clock encoder for encoding the first enable signal and the second enable signal and generating the oscillator enable signal, and an oscillator for generating the first clock signal and the second signal according to the oscillator enable signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/358,153Filed 22 Jan 2009 · division
Priority: KR 10-2006-009617529 Sep 2006
Published: US 2009/0128227 A121 May 2009
Granted: 24 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…
G11C 5/145
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…

Family

Application11/617,635Parent of this division · filed 28 Dec 2006
US 2009/0128227 A1Pre-grant publication · published 21 May 2009
US 7,499,346 B2Parent of this division
US 2008/0080287 A1Published application
US 7,623,394 B2This patent

From the US filing history. Foreign family members aren’t listed.