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US 7,623,393 B2Granted
Semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorKhil-Ohk Kang
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes: a driving controller that decodes bank activating signals to generate a plurality of driving control signals, activates some of the driving control signals, and outputs the activated driving signals; and a plurality of internal voltage generators each of which outputs an internal voltage in response to a reference voltage and the corresponding driving control signal and is disposed between two different banks among a plurality of banks.
Claims19
A semiconductor memory apparatus comprising:
- a reference voltage generator that generates a reference voltage;
- a bank activating signal generator that outputs zeroth to N-th bank activating signals for activating a plurality of banks, where N is a natural number that is equal to or greater than 1;
- a driving controller that decodes the zeroth to N-th bank activating signals to output zeroth to N-th driving control signals;
- and
- an internal voltage generator that generates an internal voltage in response to the reference voltage and the driving control signals, wherein the internal voltage generator includes a plurality of internal voltage generating units and respective ones of the internal voltage generating units are configured to correspond to respective ones of the banks,
- wherein, when at least one of the zeroth to N-th bank activating signals is activated, at least one of the zeroth to N-th driving control signals is activated,
- wherein an activated bank receives the internal voltages from the internal voltage unit of the corresponding activated bank and one of the internal voltage units of the non-selected banks.
4 more elements
A semiconductor memory apparatus comprising:
- a plurality of banks;
- a driving controller that decodes bank activating signals to generate a plurality of driving control signals, activates some of the driving control signals, and outputs activated driving control signals;
- and
- a plurality of internal voltage generating units each of which outputs an internal voltage in response to a reference voltage and a respective one of the driving control signals and is disposed between two different banks among the plurality of banks, and respective ones of internal voltage generating units correspond to respective ones of the banks,
- wherein, an activated bank receives the internal voltages from the internal voltage unit of the corresponding activated bank and the internal voltage unit of non-selected bank which is adjacent to the corresponding activated bank.
2 more elements
A semiconductor memory apparatus comprising:
- a first bank that is activated in response to a first bank activating signal;
- a second bank that is activated in response to a second bank activating signal;
- a first and second internal voltage generating units disposed adjacent to the first bank;
- and
- the first and a third internal voltage generating units disposed adjacent to the second bank,
- wherein, an activated one of the banks receives the internal voltages from an internal voltage unit of the corresponding activated bank and an internal voltage unit of an non-selected one of the banks which is adjacent to the corresponding activated bank.
3 more elements
Dependencies are inferred from the claim text.