Method of reading flash memory device for depressing read disturb
AssigneeHynix Semiconductor Inc.
InventorsNam Kyeong Kim, Ju Yeab Lee, Keum Hwan Noh
Life of this patent
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Abstract
Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.
Claims20
A method for reading a NAND flash memory device with a cell string, the cell string including a drain select transistor, a plurality of memory cells, and a source select transistor, which are all connected in series, the method comprising:
- applying a first voltage to a gate of the drain select transistor to turn on the drain select transistor;
- applying a read voltage to a gate of a selected memory cell;
- and
- applying a pass voltage to gates of unselected memory cell,
- wherein the applying of the pass voltage includes:
- applying a first pass voltage;
- and
- applying a second pass voltage after an elapse of a predetermined time following the applying of the first pass voltage, the second pass voltage having a level different from that of the first pass voltage.
A method for reading a NAND flash memory device with a cell string, the cell string including a drain select transistor, a plurality of memory cells, and a source select transistor, which are all connected in series, the drain select transistor including a cell string connected to each bit line, the method comprising:
- applying a precharge voltage to a selected bit line, the selected bit line being connected to a cell string including a selected memory cell;
- applying ground voltage to remaining bit lines except for the selected bit line;
- applying a first voltage to a gate of the drain select transistor to turn on the drain select transistor;
- applying a read voltage to a gate of a selected memory cell among the plurality of memory cells;
- and
- applying a pass voltage to each gate of unselected memory cell among the plurality of memory cells to turn on the unselected memory cell,
- wherein the applying of the pass voltage includes:
- applying a second pass voltage after an elapse of a predetermined time following the applying of the first pass voltage, the second pass voltage having a level different from that of the first pass voltage;
- applying a second voltage to a gate of the source select transistors to turn on the source select transistor;
- and
- detecting a voltage change of the selected bit line to determine whether the selected memory cell is in a programmed state or an erased state.
A method for reading a NAND flash memory device with a cell string, the cell string including a drain select transistor, a plurality of memory cells, and a source select transistor, which are all connected in series, the drain select transistor including a cell string connected to each bit line, the method comprising:
- applying a precharge voltage to a selected bit line, the selected bit line being connected to a cell string including a selected memory cell;
- applying ground voltage to remaining bit lines except for the selected bit line;
- applying a first voltage to a gate of the drain select transistor to turn on the drain select transistor;
- applying a read voltage to a gate of a selected memory cell among the plurality of memory cells;
- and
- applying a pass voltage to each gate of unselected memory cell among the plurality of memory cells to turn on the unselected memory cell,
- wherein the applying of the pass voltage includes:
- applying a second pass voltage after an elapse of a predetermined time following the applying of the first pass voltage, the second pass voltage is higher than that of the first pass voltage;
- applying a second voltage to a gate of the source select transistors to turn on the source select transistor;
- and
- detecting a voltage change of the selected bit line to determine whether the selected memory cell is in a programmed state or an erased state.
Dependencies are inferred from the claim text.