Non-volatile memory device and method of erasing the same
OwnerSeong Hun Parkinventor
Life of this patent
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Abstract
A non-volatile memory device includes planes, a control logic circuit, a high voltage generator, and a X-decoder. The planes have a plurality of memory cell blocks, respectively. The control logic circuit outputs a row address, which allows a block address to select the same memory cell blocks from different planes at substantially the same time according to an external address signal including the block address and an erase mode bit signal, and an erase instruction signal. The high voltage generator generates erase voltages for an erase operation according to the erase instruction signal. The X-decoder applies the erase voltages to memory cell blocks selected by the row address.
Claims12
A non-volatile memory device, comprising:
- a plurality of planes, each plane having a plurality of memory cell blocks;
- a control logic circuit for selecting two or more planes in the plurality planes in response to a plane select signal and an external address signal, for selecting one or more memory cell blocks in each of the selected planes in response to a plane dividing signal and the external address signal, and for selecting at least one target erase block from the selected memory cell blocks in response to a block select signal, wherein the plane select signal, the plane dividing signal and the block select signal are each input as a 2-bit signal;
- a high voltage generator to generate erase voltages for an erase operation according to an erase instruction signal;
- and
- an X-decoder to simultaneously apply the erase voltages to the one or more blocks in each of the selected planes.
A method of erasing a non-volatile memory device having a multi-plane type memory cell array, the method comprising:
- inputting a plane select signal for selecting one or more target erase planes in a plurality of planes, wherein the plane select signal is a 2-bit signal;
- inputting a plane dividing signal for selecting one or more memory cell blocks in each of the selected target erase planes, wherein the plane dividing signal is a 2-bit signal;
- inputting a block select signal for selecting at least one target erase block from the selected memory cells blocks, wherein the block select signal is a 2-bit signal;
- inputting an external address including a block address;
- generating a row address signal for selecting first memory cell blocks from the selected target erase blocks at substantially the same time according to an erase mode bit signal and the block address;
- performing an erase operation on the selected first memory cell blocks according to the row address signal;
- and
- increasing the row address after performing the erase operation.
Dependencies are inferred from the claim text.