Nonvolatile semiconductor memory device
AssigneePanasonic Corporation
InventorsYasue Yamamoto, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
Claims17
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate, comprising a plurality of MOS transistors sharing the floating gate,
- wherein the MOS transistors include:
- a first MOS transistor formed in an n-well region, one of a source and a drain of the first MOS transistor being formed by a p-type diffusion layer;
- and
- a second MOS transistor formed in an n-well region, one of a source and a drain of the second MOS transistor being formed by an n-type diffusion layer.
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate, the nonvolatile semiconductor memory device comprising a plurality of MOS transistors sharing the floating gate,
- wherein the MOS transistors include:
- a first MOS transistor formed in an n-well region, one of a source and a drain of the first MOS transistor being formed by a p-type diffusion layer;
- a second MOS transistor formed in an n-well region, one of a source and a drain of the second MOS transistor being formed by a p-type diffusion layer;
- a third MOS transistor formed in an n-well region, one of a source and a drain of the third MOS transistor being formed by an n-type diffusion layer;
- and
- a fourth MOS transistor formed by an NMOS.
Dependencies are inferred from the claim text.