Semiconductor integrated circuit device and non-volatile memory system using the same
AssigneeKabushiki Kaisha Toshiba
InventorsAtsushi Inoue, Yoshihisa Sugiura, Tatsuya Tanaka
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.
Claims20
A data writing method of a memory system including a memory controller and a non-volatile semiconductor memory being controlled by the memory controller and including a memory cell array, the data writing method comprising:
- (A) issuing a writing command by the memory controller;
- (B) receiving the writing command by the memory;
- (C) applying a writing pulse and writing data to a plurality of memory cells of the memory cell array by the memory;
- (D) verifying the data written into the plurality of memory cells;
- (E) returning a pass to the memory controller as a status by the memory if the verification passes;
- (F) determining whether or not the number of times of applying the writing pulse is equal to the number of pseudo pass issuing pulses if the verification fails;
- (G) repeating (C) to (F) if the number of times of applying the writing pulse is not equal to the number of pseudo pass issuing pulses;
- (H) determining whether or not the number of bit errors is equal to or less than a permissible bit number if the number of times of applying the writing pulse is equal to the number of pseudo pass issuing pulses;
- (I) returning a pass to the memory controller as a status by the memory if the number of bit errors is equal to or less than the permissible bit number;
- (J) determining whether or not the number of times of applying the writing pulse reaches a predetermined number if the number of bit errors exceeds the permissible bit number;
- (K) repeating (C) to (J) if the number of times of applying the writing pulse is equal to or less than the predetermined number;
- and
- (L) returning a fail to the memory controller as a status by the memory if the number of times of applying the writing pulse exceeds the predetermined number.
A memory controller which controls a non-volatile semiconductor memory including a memory cell array and a memory in which a number of pseudo pass issue pulses is written, the memory controller comprising:
- a function of issuing a writing command to cause data to be written into a plurality of memory cells in the memory cell array;
- and
- a function of issuing a rewriting command to rewrite the number of pseudo pass issuing pulses which is written in the memory.
A memory controller which controls a non-volatile semiconductor memory including a memory cell array and an issue timing control section which controls timing of issuing the pseudo pass function, the memory controller comprising:
- a function of issuing a writing command to cause data to be written into a plurality of memory cells in the memory cell array;
- and
- a function of controlling the issue timing control section.
Dependencies are inferred from the claim text.