Non-volatile memory devices and methods of programming the same
AssigneeSamsung Electronics Co., Ltd.
InventorDong-ku Kang
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs.
Claims20
A non-volatile memory device, comprising:
- a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs;
- and
- a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs,
- wherein a first page information and a second page information corresponding to a first main memory cell and a second memory cell commonly coupled to the one of the plurality main bit lines, are stored to a first flag cell coupled to a first flag bit line and a second flag cell coupled to a second flag bit line, respectively.
A method of operating a non-volatile memory device, comprising:
- arranging each of a plurality of main cells at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs;
- and
- storing page information within at least one of a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, the page information stored in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs,
- wherein a first page information and a second page information corresponding to a first main memory cell and a second memory cell commonly coupled to one of the plurality of main bit lines, are stored to a first flag cell coupled to a first flag bit line and a second flag cell coupled to a second flag bit line, respectively.
A non-volatile memory device, comprising:
- a first main cell coupled to a first word line and a first main bit line;
- a second main cell coupled to a second word line and the first main bit line;
- a first flag cell coupled to the first word line to store a first page information corresponding to the first main cell;
- a second flag cell coupled to the second word line to store a second page information corresponding to the second main cell,
- wherein the first flag cell and the second flag cell are coupled to different flag bit lines, respectively.
Dependencies are inferred from the claim text.