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US 7,623,371 B2Granted
Semiconductor device
AssigneeRenesas Technology Corp.
InventorsKazuyoshi Shiba, Yasushi Oka
Life of this patent
Estimating the term…
Abstract
p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
Claims25
A semiconductor device comprising:
- a semiconductor substrate having a first main surface and a second main surface provided on a reverse side thereof;
- a main circuit forming area disposed in the first main surface of the semiconductor substrate;
- and
- a nonvolatile memory area disposed in the first main surface of the semiconductor substrate,
- wherein the nonvolatile memory area includes:
- a first well of a first conduction type formed in the first main surface of the semiconductor substrate;
- a second well corresponding to a second conduction type well having a conduction type opposite to the first conduction type and disposed so as to be internally wrapped into the first well;
- a third well corresponding to the second conduction type well and disposed so as to be internally wrapped into the first well in a state of being electrically isolated from the second well;
- a fourth well corresponding to the second conduction type well and disposed between the second well and the third well so as to be internally wrapped into the first well in a state of being electrically isolated from the second well and the third well;
- and
- a nonvolatile memory cell disposed so as to planarly overlap with the second well, the third well and the fourth well,
- wherein the nonvolatile memory cell includes:
- a floating gate electrode disposed extending in a first direction so as to planarly overlap with the second well, the third well and the fourth well;
- a capacitive element formed at a first position where the floating gate electrode planarly overlaps with the fourth well;
- a data read field effect transistor formed at a second position where the floating gate electrode planarly overlaps with the third well;
- and
- a data write/erase element formed at a third position where the floating gate electrode planarly overlaps with the second well,
- wherein the floating gate electrode integrally has:
- a first portion that planarly overlaps with the fourth well;
- a second portion that extends from a first side of the first portion to the data read field effect transistor along the first direction;
- and
- a third portion that extends from a second side existing along the first side of the first portion to the data write/erase element along the first direction,
- said first portion being provided between the second portion and the third portion, and the second portion and the third portion being provided in a state of being shifted from each other along a second direction intersecting the first direction,
- wherein the capacitive element has:
- a first electrode formed at the first position of the first portion of the floating gate electrode;
- a first insulating film formed between the first electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the fourth well;
- and
- the fourth well,
- wherein the data read field effect transistor has:
- a second electrode formed at the second position of the second portion of the floating gate electrode;
- a second insulating film formed between the second electrode and the semiconductor substrate;
- and
- a pair of semiconductor regions of a first conduction type formed at a position where they interpose the second electrode within the third well, and
- wherein the data write/erase element has:
- a third electrode formed at the third position of the third portion of the floating gate electrode;
- a third insulating film formed between the third electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the second well;
- and
- the second well.
37 more elements
A semiconductor device comprising:
- a semiconductor substrate having a first main surface and a second main surface provided on a reverse side thereof;
- a main circuit forming area disposed in the first main surface of the semiconductor substrate;
- and
- a nonvolatile memory area disposed in the first main surface of the semiconductor substrate,
- wherein the nonvolatile memory area includes:
- a first well of a first conduction type formed in the first main surface of the semiconductor substrate;
- a second well corresponding to a second conduction type well having a conduction type opposite to the first conduction type and disposed so as to be internally wrapped into the first well;
- a third well corresponding to the second conduction type well and disposed so as to be internally wrapped into the first well in a state of being electrically isolated from the second well;
- a fourth well corresponding to the second conduction type well and disposed between the second well and the third well so as to be internally wrapped into the first well in a state of being electrically isolated from the second well and the third well;
- and
- a plurality of nonvolatile memory cells disposed so as to planarly overlap with the second well, the third well and the fourth well,
- wherein each of the nonvolatile memory cells includes:
- a floating gate electrode disposed extending in a first direction so as to planarly overlap with the second well, the third well and the fourth well;
- a capacitive element formed at a first position where the floating gate electrode planarly overlaps with the fourth well;
- a data read field effect transistor formed at a second position where the floating gate electrode planarly overlaps with the third well;
- and
- a data write/erase element formed at a third position where the floating gate electrode planarly overlaps with the second well,
- wherein the floating gate electrode integrally has:
- a first portion that planarly overlaps with the fourth well;
- a second portion that extends from a first side of the first portion to the data read field effect transistor along the first direction;
- and
- a third portion that extends from a second side existing along the first side of the first portion to the data write/erase element along the first direction,
- said first portion being provided between the second portion and the third portion, and the second portion and the third portion being provided in a state of being shifted from each other along a second direction intersecting the first direction,
- wherein the capacitive element has:
- a first electrode formed at the first position of the first portion of the floating gate electrode;
- a first insulating film formed between the first electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the fourth well;
- and
- the fourth well,
- wherein the data read field effect transistor has:
- a second electrode formed at the second position of the second portion of the floating gate electrode;
- a second insulating film formed between the second electrode and the semiconductor substrate;
- and
- a pair of semiconductor regions of a first conduction type formed at a position where they interpose the second electrode within the third well, and
- wherein the data write/erase element has:
- a third electrode formed at the third position of the third portion of the floating gate electrode;
- a third insulating film formed between the third electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the second well;
- and the second well.
36 more elements
A semiconductor device comprising:
- a semiconductor substrate having a first main surface and a second main surface provided on a reverse side thereof;
- a main circuit forming area disposed in the first main surface of the semiconductor substrate;
- and
- a nonvolatile memory area disposed in the first main surface of the semiconductor substrate,
- wherein the nonvolatile memory area includes:
- a first well of a first conduction type formed in the first main surface of the semiconductor substrate;
- a second well corresponding to a second conduction type well having a conduction type opposite to the first conduction type and disposed so as to be internally wrapped into the first well;
- a third well corresponding to the second conduction type well and disposed so as to be internally wrapped into the first well in a state of being electrically isolated from the second well;
- a fourth well corresponding to the second conduction type well and disposed between the second well and the third well so as to be internally wrapped into the first well in a state of being electrically isolated from the second well and the third well;
- and
- a plurality of nonvolatile memory cells disposed so as to planarly overlap with the second well, the third well and the fourth well,
- wherein each of the nonvolatile memory cells includes:
- a floating gate electrode disposed extending in a first direction so as to planarly overlap with the second well, the third well and the fourth well;
- a capacitive element formed at a first position where the floating gate electrode planarly overlaps with the fourth well;
- a data read field effect transistor formed at a second position where the floating gate electrode planarly overlaps with the third well;
- and
- a data write/erase element formed at a third position where the floating gate electrode planarly overlaps with the second well,
- wherein the floating gate electrode integrally has:
- a first portion that planarly overlaps with the fourth well;
- a second portion that extends from a first side of the first portion to the data read field effect transistor along the first direction;
- and
- a third portion that extends from a second side existing along the first side of the first portion to the data write/erase element along the first direction,
- said first portion being provided between the second portion and the third portion, and the second portion and the third portion being provided in a state of being shifted from each other along a second direction intersecting the first direction,
- wherein the capacitive element has:
- a first electrode formed at the first position of the first portion of the floating gate electrode;
- a first insulating film formed between the first electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the fourth well;
- and
- the fourth well,
- wherein the data read field effect transistor has:
- a second electrode formed at the second position of the second portion of the floating gate electrode;
- a second insulating film formed between the second electrode and the semiconductor substrate;
- and
- a pair of semiconductor regions of a first conduction type formed at a position where they interpose the second electrode within the third well,
- wherein the data write/erase element has:
- a third electrode formed at the third position of the third portion of the floating gate electrode;
- a third insulating film formed between the third electrode and the semiconductor substrate;
- a second conduction type semiconductor region formed within the second well;
- and
- the second well,
- wherein of the nonvolatile memory cells, the nonvolatile memory cells arranged side by side along the first direction are disposed so as to be symmetrical with respect to one another, and
- wherein the data write/erase elements of the nonvolatile memory cells arranged side by side along the first direction are formed in the second well common thereto.
39 more elements
Dependencies are inferred from the claim text.