US 7,623,364 B2Granted

Semiconductor device

AssigneeRenesas Technology Corp.

InventorsToshio Sasaki, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori

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Abstract

A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

Claims23

Dependent claims

A semiconductor device including a semiconductor chip having a core region and an input/output region formed outside the core region, so arranged that at least an operation part and a memory for holding data from the operation part are formed in the core region, and an input/output circuit for inputting/outputting data between the operation part or the memory formed in the core region and an external source is formed in the input/output region,

wherein the semiconductor chip includes:
(a) a first wire for supplying power supply potential to the operation part and the memory;
(b) a second wire for supplying a potential lower than the power supply potential to the operation part;
(c) a third wire for supplying a potential lower than the power supply potential to the memory;
(d) a reference wire for supplying reference potential;
(e) a first switch for electrically coupling and decoupling the second wire and the reference wire to and from each other;
(f) a second switch for electrically coupling and decoupling the third wire and the reference wire to and from each other;
(g) a plurality of first pads electrically coupled with the first wire;
and
(h) a plurality of second pads electrically coupled with the reference wire, and
wherein the first pads and the second pads are formed in the core region and the first switch and the second switch are also formed in the core region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/016,201Filed 17 Jan 2008
Priority: JP 2007-09136530 Mar 2007
Published: US 2008/0239780 A12 Oct 2008
Granted: 24 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 5/145
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
H10W 72/50
Interconnections or connectors in packages: bond wires
H10W 72/5524
Comprising metals or metalloids, e.g. silver: comprising aluminium [Al]