Thin film transistor array panel used for a liquid crystal display and a manufacturing method thereof

A thin film transistor array panel used for a liquid crystal display, comprising:

• a substrate;
• a gate line formed on the substrate and extending in a first direction;
• a gate electrode coupled to the gate line;
• a gate insulating layer covering the gate line and the gate electrode;
• a semiconductor layer on the gate insulating layer;
• a doped semiconductor layer on the semiconductor layer;
• a data line formed on the doped semiconductor layer, extending in a second direction and intersecting the gate line;
• a source electrode coupled to the data line;
• a drain electrode facing the source electrode with a gap therebetween on the semiconductor layer;
• a passivation layer covering the data line and the source electrode and part of the drain electrode;
• and
• a pixel electrode coupled to the drain electrode,
• wherein substantially the whole area of the data line is formed on the doped semiconductor layer and the doped semiconductor layer is formed only below the data line, the source electrode, and the drain electrode.

A thin film transistor array panel used for a liquid crystal display, comprising:

• a substrate;
• a gate line formed on the substrate and extending in a first direction;
• a gate electrode coupled to the gate line;
• a gate insulating layer covering the gate line and the gate electrode;
• a semiconductor layer on the gate insulating layer;
• a doped semiconductor layer on the semiconductor layer;
• a data line formed on the doped semiconductor layer, extending in a second direction and crossing over the gate line;
• a source electrode electrically coupled to the data line;
• a drain electrode facing the source electrode with a gap therebetween;
• a passivation layer covering the data line and the source electrode and a part of the drain electrode;
• and
• a pixel electrode electrically coupled to the drain electrode,
• wherein substantially the whole area of the data line is formed on the semiconductor layer and the doped semiconductor layer is formed only below the data line, the source electrode, and the drain electrode.