Synchronization control apparatus and method
AssigneeRealtek Semiconductor Corp.
InventorsChing-Tzong Wang, Szu-Ping Chen
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Abstract
A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal.
Claims13
A synchronization control apparatus for driving a display module in an interlaced scan mode, the synchronization control apparatus comprising:
- a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal;
- a first multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal;
- a second multiplexer coupled to the first multiplexer for selecting one of a first data corresponding to a first function and a second data corresponding to a second function as a third data according to the odd/even field indication signal;
- and
- a convolution circuit coupled to the second multiplexer for performing a convolution operation according to an input video data and the third data to generate an output video data to be utilized for driving the display module.
A synchronization control method for driving a display module in an interlaced scan mode, the synchronization control method comprising:
- delaying an input vertical sync (IVS) signal to generate a delayed signal;
- selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal;
- selecting one of a first data corresponding to a first function and a second data corresponding to a second function as a third data according to the odd/even field indication signal;
- and
- performing a convolution operation according to an input video data and the third data to generate an output video data to be utilized for driving the display module.
A display control apparatus comprising:
- a video processing circuit for receiving an interlaced scan video signal to perform video processing;
- a selection signal generation circuit for generating a selection signal;
- a delay circuit for receiving an input vertical sync (IVS) signal corresponding to the interlaced scan video signal, and delaying the IVS signal to generate a delayed signal;
- and
- a multiplexer coupled to the delay circuit and the selection signal generation circuit for selecting one of the IVS signal and the delayed signal according to the selection signal to generate an output vertical sync (OVS) signal;
- wherein a value of the selection signal corresponds to an interval between pulses of the IVS signal and the video processing circuit is utilized for performing a convolution operation on the interlaced scan video signal.
Dependencies are inferred from the claim text.