Systems for displaying images by utilizing horizontal shift register circuit for generating overlapped output signals

A system for displaying images comprising:

• a horizontal shift register (HSR) circuit operative to generate overlapped output signals, the HSR circuit comprising:
• a plurality of dynamic shift registers connected in a series, each dynamic shift register comprising:
• a first switching circuit, coupled to a first input terminal of the dynamic shift register, an output terminal of the dynamic shift register, a first supply voltage and a first node, and operative to control if the first supply voltage is transmitted to the first node according to a first input signal received by the first input terminal and an output signal outputted from the output terminal;
• a level adjusting circuit, coupled to and located between the first node and a second supply voltage, wherein when the first switching circuit is switched off, the level adjusting circuit is capable of driving a voltage level of the first node toward the second supply voltage;
• a second switching circuit, coupled to the first node, the first supply voltage, and a second node, and operative to control if the first supply voltage is transmitted to the second node according to the voltage level of the first node;
• a third switching circuit, coupled to the first input signal and the second node, and operative to control if the first input signal is transmitted to the second node according to the first input signal;
• a fourth switching circuit, coupled to the first node, the first supply voltage, and the output terminal, and operative to control if the first supply voltage is transmitted to the output terminal according to the voltage level of the first node;
• and
• a fifth switching circuit, coupled to a second input terminal of the dynamic shift register, the second node, and the output terminal, and operative to control if the second input signal received by the second input terminal is transmitted to the output terminal according to a voltage level of the second node;
• wherein each dynamic shift register has the first input terminal coupled to an output terminal of a preceding dynamic shift register except an initial dynamic shift register.