US 7,623,109 B2Granted

Display device

AssigneeHitachi Displays, Ltd.

InventorsHideo Sato, Shigeyuki Nishitani, Toshio Miyazawa

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Abstract

The present invention provides a display device which is capable of fetching input signals of a small amplitude into the inside thereof. A level converting circuit includes a first-conductive-type first transistor having a gate electrode to which input signals are applied through a first capacitive element, a second-conductive-type second transistor having a gate electrode to which input signals are applied through a second capacitive element, a first bias circuit which applies a first bias voltage to the gate electrode of the first transistor and a second bias circuit which applies a second bias voltage to the gate electrode of the second transistor. Here, the first bias voltage is a voltage which turns off the first transistor when a voltage applied to the gate electrode of the first transistor assumes a maximum value and the second bias voltage is a voltage which turns off the second transistor when a voltage applied to the gate electrode of the second transistor assumes a minimum value.

Claims6

Dependent claims

A display device having a level converting circuit which converts input signals having a small amplitude into signals having a larger amplitude,

wherein the level converting circuit comprises:
a sample-hold circuit which samples the input signals;
a transistor comprising a gate electrode to which an output voltage of the sample-hold circuit is inputted;
a first switching element of which a first electrode is connected to a first power line supplying a first power source voltage;
a second switching element of which a first electrode is connected to a second electrode of the first switching element, and of which a second electrode is connected to a second electrode of the transistor;
a voltage holding circuit connected to the first electrode of the second switching element;
an inverter circuit connected to the first power line and a second power line which supplies a second power source voltage, and to which an output voltage from the voltage holding circuit is inputted;
and
a bias circuit connected to the second power line, and which provides a bias voltage to a first electrode of the transistor, the bias voltage decreasing a threshold voltage of the transistor.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/514,841Filed 5 Sep 2006 · continuation
Priority: JP 2002-37715026 Dec 2002
Published: US 2007/0001985 A14 Jan 2007
Granted: 24 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G09G 3/3611
Using liquid crystals: control of matrices with row and column drivers
H03K 19/018571
Coupling arrangements; Impedance matching circuits: of complementary type, e.g. CMOS
G09G 2310/0289
Details of driving circuits: details of voltage level shifters arranged for use in a driving circuit
G09G
Arrangements or circuits for control of indicating devices using static means to

Family

Application10/725,593Parent of this continuation · filed 3 Dec 2003
US 2007/0001985 A1Pre-grant publication · published 4 Jan 2007
US 7,123,237 B2Parent of this continuation
US 2004/0125102 A1Published application
US 7,623,109 B2This patent

From the US filing history. Foreign family members aren’t listed.