Digital calibration loop for an analog to digital converter
AssigneeBroadcom Corporation
InventorsMichael Le, Chun-Ying Chen, Wynstan Tong, Kwang Young Kim, Hui Pan
Life of this patent
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Abstract
A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.
Claims32
An analog-to-digital conversion circuit, comprising:
- an analog-to-digital converter (ADC) having a first input, a second input, and an output;
- a multiplexer coupled to said first ADC input;
- a variable voltage source coupled to said second ADC input;
- and
- a calibration circuit to control said variable voltage source, and coupled between said variable voltage source and said ADC output,
- wherein the ADC is configured to compare a fixed voltage supplied via said multiplexer with a variable voltage supplied by said variable voltage source.
A method for countering an analog-to-digital converter (ADC) offset voltage to calibrate an analog-to-digital converter, comprising:
- comparing a fixed voltage to a variable voltage with the ADC to determine an ADC offset voltage and produce an ADC output;
- integrating said ADC output at least once to provide a control signal;
- and
- varying said variable voltage with said control signal to counter the ADC offset voltage,
- wherein said ADC output includes at least one of a logic high and a logic low signal and wherein said varying causes a ratio of said logic high signal to said logic low signal to substantially equal one.
An analog-to-digital conversion circuit, comprising:
- means for comparing a fixed voltage to a variable voltage with an analog-to-digital converter (ADC) to determine an offset voltage;
- said means including:
- a reference ladder having a plurality of taps that generate a plurality of reference voltages, including a fixed center tap reference voltage;
- a first multiplexer having a first input configured to receive an analog signal and a second input coupled to said fixed center tap reference voltage;
- a second multiplexer coupled to an output of said reference ladder for selecting one of said plurality of reference voltages as a variable calibration reference voltage;
- and
- an analog-to-digital converter (ADC) having an analog signal input coupled to an output of said first multiplexer, and a reference signal input coupled to an output of said second multiplexer,
- wherein during calibration, said first multiplexer is configured to couple said fixed center tap reference voltage to said analog signal input of said ADC;
- and
- means for varying said variable voltage to counter said offset voltage.
A method of mitigating a DC offset in a multi-bit analog to digital converter (ADC), each bit of said multi-bit ADC having an analog signal input and a reference voltage input, said reference voltage input selectively coupled to a plurality of reference voltages selectable from a plurality of taps, comprising the steps of:
- during a calibration mode,
- (1) providing an uncalibrated reference voltage to said analog signal input of said ADC from a center tap of said plurality of reference voltages;
- (2) providing a calibration reference voltage to said reference voltage input from a second tap of said plurality of reference voltages;
- (3) incrementally adjusting said calibration reference voltage until said ADC indicates that said offset voltage is calibrated;
- and
- (4) repeating steps (1)-(3) for each bit of said multi-bit ADC, resulting in a plurality of calibration reference voltages.
A multi-bit conversion circuit with DC offset calibration, each bit of said conversion circuit comprising:
- a reference ladder having a plurality of taps that generate a plurality of reference voltages, including a center tap reference voltage;
- a first multiplexer having a first input configured to receive an analog signal and a second input coupled to said center tap reference voltage;
- a second multiplexer coupled to an output of said reference ladder for selecting one of said plurality of reference voltages as a calibration reference voltage;
- and
- an analog-to-digital converter (ADC) having an analog signal input coupled to an output of said first multiplexer, and a reference signal input coupled to an output of said second multiplexer;
- wherein during calibration, said first multiplexer is configured to couple said center tap reference voltage to said analog signal input of said ADC.
Dependencies are inferred from the claim text.