Multi-loop phase locked loop circuit

A phase locking method, comprising:

• detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal;
• generating a first control current according to the first difference signal;
• detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal;
• generating a second control current according to the second difference signal;
• generating a control signal according to at least one of the first control current and the second control current;
• generating a first oscillating signal according to the control signal;
• and
• utilizing the first reference clock signal to generate a second oscillating signal after the first oscillating signal is locked to the second reference clock signal.

A multi-loop phase locked loop apparatus, comprising:

• a feedback clock signal generating module, for generating a first feedback clock signal and a second feedback clock signal;
• a first loop, for detecting the difference between the first feedback clock signal and a first reference clock to generate a first loop signal;
• a second loop, for detecting the difference between the second feedback clock signal and a second reference clock to generate a second loop signal;
• and
• a control unit, for choosing one of the first loop signal and the second loop signal to be the feedback clock signal, wherein the feedback clock signal generating module generates the first feedback clock signal and the second a computing unit, for computing a time parameter, wherein the control unit switches the original used loop to the other loop if the time parameter reaches a predetermined value.

A multi-loop phase locked loop apparatus, comprising:

• a first loop, comprising:
• a first phase/frequency detector, for detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal;
• and
• a first charge pump, coupled to the first phase/frequency detector, for generating a first control current according to the first difference signal;
• a second loop, comprising:
• a second phase/frequency detector, for detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal;
• and
• a second charge pump, coupled to the second phase/frequency detector, for generating a second control current according to the second difference signal;
• a loop filter, coupled to the first charge pump and the second charge pump, for generating a control signal;
• a voltage control oscillator, coupled to the loop filter, for generating an oscillating signal according to the control signal;
• a first frequency divider, coupled to the voltage control oscillator and the first phase/frequency detector, for frequency-dividing the oscillating signal to generate the first feedback clock signal;
• a second frequency divider, coupled to the voltage control oscillator and the second phase/frequency detector, for frequency-dividing the oscillating signal to generate the second feedback clock signal;
• and
• a control circuit, coupled to the first loop and the second loop, for switching between the first loop and the second loop to generate the control signal according to at least one of the first control current, the second control current and the control signal, wherein the control circuit turns off the second loop and turns on the first loop after the multi-loop phase locked loop apparatus is locked to the second reference clock signal.

A multi-loop phase locked loop apparatus, comprising:

• a first loop, comprising:
• a first phase/frequency detector, for detecting a difference between a first feedback clock signal and a first reference clock signal to output a first difference signal;
• and
• a first charge pump, coupled to the first phase/frequency detector, for generating a first control current according to the first difference signal;
• a second loop, comprising:
• a second phase/frequency detector, for detecting a difference between a second feedback clock signal and a second reference clock signal to output a second difference signal;
• and
• a second charge pump, coupled to the second phase/frequency detector, for generating a second control current according to the second difference signal;
• a loop filter, coupled to the first charge pump and the second charge pump, for generating a control signal;
• a voltage control oscillator, coupled to the loop filter, for generating an oscillating signal according to the control signal;
• a first frequency divider, coupled to the voltage control oscillator and the first phase/frequency detector, for frequency-dividing the oscillating signal to generate the first feedback clock signal;
• a second frequency divider, coupled to the voltage control oscillator and the second phase/frequency detector, for frequency-dividing the oscillating signal to generate the second feedback clock signal;
• a control circuit, coupled to the first loop and the second loop, for switching between the first loop and the second loop to generate the control signal according to at least one of the first control current, the second control current and the control signal;
• and
• a monitoring circuit, for monitoring the value of the first control current and the second control current or, wherein if the control signal is stable, the control circuit switches the first loop or the second loop.

A multi-loop phase locked loop apparatus, comprising:

• a feedback clock signal generating module, for generating a first feedback clock signal and a second feedback clock signal;
• a first loop, for detecting the difference between the first feedback clock signal and a first reference clock to generate a first loop signal;
• a second loop, for detecting the difference between the second feedback clock signal and a second reference clock to generate a second loop signal;
• and
• a control unit, for choosing one of the first loop signal and the second loop signal to be the feedback clock signal, wherein the feedback clock signal generating module generates the first feedback clock signal and the second a computing unit, for computing a time parameter, wherein the control unit switches the original used loop to the other loop if the time parameter reaches a predetermined value;
• a monitoring circuit, for monitoring the value of a first control current and a second control current, or if a control signal is stable, the control unit switches the first or the second loop.