Power amplifier circuit having a bias signal inputted into input terminal and method thereof
AssigneeRealtek Semiconductor Corp.
InventorRen-Chieh Liu
Life of this patent
Estimating the term…
Loading patent…
AssigneeRealtek Semiconductor Corp.
InventorRen-Chieh Liu
Estimating the term…
The present invention discloses an adjustable gain power amplifier circuit. The adjustable gain power amplifier circuit includes a power amplifying unit for receiving and amplifying an input signal to generate an output signal; a power detecting unit for detecting power of the input signal to generate a detecting signal; and a biasing control unit for generating a biasing signal according to the detecting signal and to output the biasing signal.
An adjustable gain power amplifier circuit, comprising:
An adjustable gain power amplifier circuit, comprising:
An adjustable gain power amplifier circuit, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
In high-frequency amplifiers or in frequency-changers: in modulators, frequency-changers, transmitters or power amplifiers
With control of the polarisation voltage or current, e.g. gliding Class A: by using a signal derived from the input signal
Using continuously variable impedance elements: using field-effect transistors [FET]
Control of amplification
About 1 year of term left · ends 7 Nov 2027 (estimated)
1. Field of the Invention
The present invention is related to a power amplifying circuit, and more particularly to a power amplifying circuit having a biasing signal at the input terminal, and an amplifying method thereof.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating an adjustable gain power amplifier circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating the relationship between the power of the output signal and the operating gain of the power amplifying unit in FIG. 1.
FIG. 3 is a diagram illustrating the relationship between the power of the output signal and the DC current of the power amplifying unit in FIG. 1.
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating an adjustable gain power amplifier circuit 100 according to a first embodiment of the present invention. The power amplifier circuit 100 includes a power amplifying unit 102, a power detecting unit 104, and a biasing control unit 106. The power detecting unit 104 is coupled to an input signal fin, and the biasing control unit 106 is coupled to the power detecting unit 104 and an input terminal N2 of the power amplifying unit 102. The power amplifier circuit 100 further includes a capacitor Cc coupled between an input terminal N1 of the power amplifier circuit 100 and the power amplifying unit 102. The power amplifying unit 102 performs power amplifying of the input signal fin that is received at the input terminal N2 and outputs an output signal fout at the output terminal N3 (which is the output terminal of the power amplifier circuit 100). The power detecting unit 104 is utilized for detecting the power of the input signal fin to generate a detecting signal. The biasing control unit 106 is utilized for generating a biasing signal according to the detecting signal, and outputting the biasing signal to the input terminal N2 of the power amplifying unit 102.
According to the embodiment shown in FIG. 1, the input terminal N2 of the power amplifying unit 102 is coupled to the gate terminal of an internal N-type transistor of the power amplifying unit 102. Furthermore, the power amplifying unit 102 consists of a predetermined voltage source Vdd (fixed DC biasing current) and a ground terminal GND. Therefore, the DC biasing current at the input terminal N2 will decide the operating gain of the power amplifying unit 102. The power detecting unit 104 includes a capacitor Cin coupled to the input terminal N1, and the other terminal of the capacitor Cin is coupled to the gate terminal of a N-type transistor M1. In order to precisely detect the power of the input signal fin, the gate terminal of the N-type transistor M1 of the power amplifier circuit 100 is biased at the pinch-off voltage. The biasing control unit 106 includes a current mirror that consists of two P-type transistors M2, M3, a diode connected N-type transistor M4, and an inductor Lin. Please note that, in another embodiment of the present invention, the power amplifier further consists of a matching circuit in order to match the impedance between the output terminal N3 of the power amplifying unit 102 and the matching circuit, which also belongs to the scope of the present invention.