Data holding circuit and signal processing circuit

A data holding circuit comprising:

• two flip-flops and four exclusive OR circuits,
• wherein
• input ends of a first exclusive OR circuit receive an input signal and an output signal from a fourth exclusive OR circuit, respectively,
• input ends of a second exclusive circuit receive an output signal from the first exclusive OR circuit and an output signal from a first flip-flip, respectively,
• input ends of a third exclusive OR circuit receive the output signal from the first exclusive OR circuit and an output signal from a second flip-flop, respectively;
• an input terminal of the first flip-flop receives an output signal from the second exclusive OR circuit and a clock terminal of the first flip-flop receives a clock signal, and the first flip-flop outputs input data that is input to the input terminal thereof from an output terminal thereof at a rising edge timing of the clock signal while holding the input data therein;
• an input terminal of the second flip-flop receives an output signal from the third exclusive OR circuit, a clock terminal of the second flip-flop receives an inverted signal of the clock signal, and the second flip-flop outputs input data that is input to the input terminal thereof from an output terminal thereof at a falling edge timing of the clock signal while holding the input data therein, and
• input ends of the fourth exclusive OR circuit receive the output signals from the first flip-flop and the second flip-flop, respectively, an output signal from the fourth exclusive OR circuit is output as an output result, and the input signal is latched at both the rising edge timing and the falling edge timing of the clock signal.