Ramped clock digital storage control

A method of controlling a digital system having an input stage coupled at a dynamic output node to a static memory stage having an operational state, the method comprising the steps of:

• providing a data signal and a control signal as inputs for the input stage;
• providing a ramped clock signal for the input stage, the ramped clock signal defining when an update of the operational state can occur in accordance with the data signal;
• and,
• operating a switch coupled to the dynamic output node and responsive to the control signal to prevent the update of the operational state without decoupling the ramped clock signal from the input stage.

A method of controlling a memory cell of a digital system, the memory cell having an input stage coupled at a dynamic node to a static memory stage having an operational state based on a data signal, the method comprising the steps of:

• providing the data signal and a control signal as inputs for the input stage;
• providing a ramped clock signal for the input stage, the ramped clock signal providing timing information for the memory cell to define when an update of the operational state can occur;
• operating a switch coupled to the dynamic output node and responsive to the control signal to prevent the update of the operational state;
• and
• continuing the ramped clock signal providing step during the operating step to facilitate recovery of clock signal energy from the digital system.