Circuit having a local power block for leakage reduction

#The present disclosure relates generally to methods and systems for reducing leakage current in circuit design, and more specifically, to methods and systems for reducing leakage current in low activity circuitry while maintaining the performance of high activity circuitry.

#With feature size becoming smaller in circuit design, power leakage is becoming a more significant portion of the overall power consumed by a circuit, such as a sequential circuit. Power leakage in circuit design is an important issue, particularly because power leakage can account for a significant proportion of the total power for an IC.

#For example, FIG. 1 illustrates a conventional device (e.g., inverter) 100 having an input a, an output nz, a voltage source, and ground. A capacitor 102 is charged by the supply current Vdd. Theoretically, once the capacitor 102 is charged, there will be no current flowing through the circuit and there will be no power leakage through the circuit. However, this may not be true in practice, since devices may leak. Even though a device is supposed to be turned off or inactive there can still be some current flowing/leakage through the device. Hence, there will be power leakage through the device.

#The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.

#FIG. 1 is a schematic illustrating a conventional inverter circuit.

#FIG. 2 is a schematic illustrating one embodiment of a circuit having a local power block configured to decouple a second portion operating at a low operating frequency.

#Aspects of the invention are disclosed in the following description and related drawings directed to exemplary embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the aspects of the invention. Additionally, well known elements of the embodiments of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the exemplary embodiments of the invention.

#The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the terms “embodiments” or “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

#The exemplary embodiments recognize and/or account for the distinctions between portions of a circuit operating at a low operating frequency and portions of the circuit operating at a high operating frequency. For example, one embodiment can include a circuit having a first and second portion. The embodiment can further include a local power block (e.g., a local header or local footer) configured to decouple only those portions of the circuit that are not high performance (i.e., portions of the circuit that are configured to operate at a low operating frequency or that are configured for lower activity), instead of having a global header or footer for all parts of the circuit.