Delay locked loop circuits and methods of generating clock signals

A delay locked loop circuit comprising:

• a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal;
• a control voltage generator configured to output a control voltage based on the comparison signal;
• a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal;
• and
• a control voltage initializer which includes a first set of delay elements and a second set of delay elements, and which is configured to generate first and second digital codes based on characteristics of the first and second sets of delay elements, and to generate an initial control voltage based on the first and second digital codes,
• wherein the characteristics of the first set of delay elements are based on a minimum delay voltage which minimizes a delay of the reference clock signal, and the characteristics of the second set of delay elements are based on a maximum delay voltage which maximizes the delay of the reference clock signal.

A delay locked loop circuit comprising:

• a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal;
• a control voltage generator configured to output a control voltage based on the comparison signal;
• a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal;
• and
• a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes,
• wherein the control voltage initializer generates the initial control voltage based on a minimum delay voltage which minimizes a delay of the reference clock signal, and a maximum delay voltage which maximizes the delay of the reference clock signal, and
• wherein the voltage controlled delay line comprises L first delay elements connected in series, where L is a natural number, and wherein the control voltage initializer comprises:
• a reference clock divider configured to divide the reference clock signal by K and to output a divided reference clock signal, where K is 2 or a natural number greater than 2;
• a first replica voltage controlled delay line comprising M second delay elements connected in series and configured to receive the reference clock signal and to output first reference clock delay signals from the respective M second delay elements in response to the minimum delay voltage, where M is a natural number;
• a second replica voltage controlled delay line comprising N third delay elements connected in series and configured to receive the reference clock signal and to output second reference clock delay signals from the respective N third delay elements in response to the maximum delay voltage, where N is a natural number;
• a code generator configured to generate and output an initial voltage digital code based on the divided reference clock signal, the first reference clock delay signals, and the second reference clock delay signals;
• and
• an initial control voltage generator configured to generate the initial control voltage in response to the initial voltage digital code.

A method of generating a clock signal in a delay locked loop circuit, the method comprising:

• comparing a phase of a reference clock signal with a phase of an output clock signal, and outputting a comparison signal;
• outputting a pre-control voltage based on the comparison signal;
• generating an initial control voltage based on first and second digital codes generated in response to the reference clock signal, a minimum delay voltage, and a maximum delay voltage, wherein the reference clock signal and the minimum delay voltage is applied to a first set of delay elements, and the reference clock signal and the maximum delay voltage are applied to a second set of delay elements;
• and
• outputting the output clock signal by delaying the reference clock signal in response to one of the pre-control voltage and the initial control voltage.

A method of generating a clock signal in a delay locked loop circuit, the method comprising:

• comparing a phase of a reference clock signal with a phase of an output clock signal, and outputting a comparison signal;
• outputting a pre-control voltage based on the comparison signal;
• generating an initial control voltage based on a digital code generated in response to the reference clock signal, a minimum delay voltage, and a maximum delay voltage;
• and
• outputting the output clock signal by delaying the reference clock signal in response to one of the pre-control voltage and the initial control voltage,
• wherein generating the initial control voltage comprises:
• outputting a divided reference clock signal by dividing the reference clock signal;
• outputting first reference clock delay signals having different phases by delaying the reference clock signal in response to the minimum delay voltage;
• outputting second reference clock delay signals having different phases by delaying the reference clock signal in response to the maximum delay voltage;
• generating a first digital code and a second digital code by sampling the divided reference clock signal with the first reference clock delay signals and the second reference clock delay signals;
• comparing the first digital code and the second digital code with a locking digital code and generating an initial voltage digital code;
• and
• generating the initial control voltage based on the initial voltage digital code.