Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency

A circuit for generating an output clock signal from an input clock signal having a clock frequency, comprising:

• a loop, comprising:
• a detector circuit for outputting a representation of a phase difference between the input clock signal and the output clock signal,
• delay circuitry for receiving the representation of the phase difference, and for outputting the output clock signal, and
• a controller for sending at least one signal to the detector circuit to selectively enable the detector circuit, wherein the controller comprises a counter for determining a value indicative of the loop frequency during a loop measurement period, and wherein the controller derives the at least one signal by frequency dividing the input clock signal by the value.

A circuit for generating an output clock signal from an input clock signal having a clock frequency, comprising:

• a loop, comprising in series:
• a detector circuit for outputting a representation of a phase difference between the input clock signal and a delayed version of the output clock signal,
• a variable delay circuit for receiving the representation of the phase difference, and for outputting the output clock signal, wherein the output clock signal has the clock frequency, and
• a fixed delay circuit for receiving the output clock signal and for outputting the delayed version of the output clock signal, wherein the delayed version of the output clock signal has the clock frequency;
• and
• a controller for sending a signal to the detector circuit to selectively enable the detector circuit, wherein the controller selectively enables the detector circuit in accordance with a frequency lower than the clock frequency but higher than or substantially equal to a loop frequency, wherein the loop frequency determined in accordance with a propagation delay through the loop.

A circuit for generating an output clock signal from an input clock signal having a clock frequency, comprising:

• a loop, comprising in series:
• a detector circuit for outputting a representation of a phase difference between the input clock signal and a delayed version of the output clock signal,
• a variable delay circuit for receiving the representation of the phase difference, and for outputting the output clock signal, wherein the output clock signal has the clock frequency, and
• a fixed delay circuit for receiving the output clock signal and for outputting the delayed version of the output clock signal, wherein the delayed version of the output clock signal has the clock frequency;
• and
• a controller for sending a signal to the detector circuit to selectively enable the detector circuit, wherein the controller comprises a counter for determining the loop frequency as a value during a loop measurement period.