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US 7,622,969 B2Granted
Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock
AssigneeMicron Technology, Inc.
InventorGary M. Johnson
Life of this patent
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AssigneeMicron Technology, Inc.
InventorGary M. Johnson
Estimating the term…
Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider operably coupled to the delayed clock signal and configured to generate a frequency divided clock signal. Furthermore, the delay locked loop may include a phase detector configured to receive the reference clock signal and the frequency divided clock signal having a frequency less than that of the reference clock signal. Additionally, the phase detector may be configured to measure a phase difference of the reference clock signal and the frequency divided clock signal upon receipt of an active edge of the frequency divided clock signal.
A delay locked loop, comprising:
A method of operating a delay locked loop, comprising the acts of:
A method of operating a delay locked loop, comprising the acts of:
A semiconductor device, comprising:
An electronic system, comprising:
Dependencies are inferred from the claim text.