Delay locked loop
AssigneeNanya Technology Corporation
InventorWei-Li Liu
Life of this patent
Estimating the term…
Abstract
In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.
Claims7
A delay locked loop, for delaying an input signal into an output signal, comprising:
- a phase detector, for comparing a phase relationship between the input signal and the output signal to output a phase comparison result;
- an independent control unit, for generating a control signal independent from the input signal and the output signal according to a clock information signal;
- a delay line, for delaying the input signal, wherein the delay line comprises a plurality of unit delay elements connected in series, a value of unit delay of each of the unit delay elements is adjusted by a control signal generated by the control unit, and
- a multiplexer, for selecting a number of delay stages of the unit delay elements according to the phase comparison result provided by the phase detector to generate the output signal.
Dependencies are inferred from the claim text.