Switchable phase locked loop and method for the operation of a switchable phase locked loop

A method for the operation of a phase locked loop (12), wherein a controllable oscillator (DCO) generates an output clock (CKout) of the phase locked loop and can be switched over between a first clock signal (Ckin1) and a second clock signal (CKin2) for use as an input clock of the phase locked loop, the phase locked loop including first and second phase detectors (PD1 and PD2) each operable in either a first or a second operating mode,

• comprising the steps:
• (a) in the first operating mode, for the clock signal (Ckin1 or CKin2) currently being used to generate the output clock (CKout), determining a first-mode phase difference between this clock signal and a first phase-shift adjusted version (CK<1:8>) of the output clock (CKout), and using the first-mode phase difference for the control of the oscillator (DCO) in generating the output clock (CKout), (b) in the second operating mode, for the clock signal (CKin2 or Ckin1) currently not being used to generate the output clock (CKout), adjusting the phase shift of a second phase-shift adjusted version (CK<1:8> of the output signal (CKout), and determining the frequency difference of the clock signal (CKin2 or Ckin1) currently not being used with respect to the output clock (CKout) and storing and continuously updating the frequency difference, and (c) providing the stored frequency difference as a frequency adaptation control signal (IN_OUT) for the control of the oscillator (DCO) after the switch-over to this clock signal (CKin2 or CKin1) previously not being used, so that any frequency jump during switch-over produces, by means of the frequency adaptation control signal (INT_OUT), a substantially immediate corresponding frequency adjustment of the oscillator (DCO), wherein, in the second operating mode, the phase-shift adjusted version (CK<1:8>) of the output clock signal (CKout) is adjusted on the basis of the frequency adaptation control signal.

A phase locked loop (12) with a controllable oscillator (DCO) for generating an output clock (CKout) of the phase locked loop and with a switch-over device (22) for switching over between a first clock signal (Ckin1) and a second clock signal (CKin2) for use as an input clock of the phase locked loop,

• comprising:
• (a) at least two phase detectors (PD1, PD2) which can be switched between different operating modes are provided respectively for the at least two input clock signals (Ckin1, CKin2), such that the phase detector (PD1 or PD2) for the clock signal (Ckin1 or CKin2) currently being used as the input clock is put into a first operating mode and the phase detector (PD2 or PD1) for the clock signal (CKin2 or Ckin1) currently not being used as the input clock is put into a second operating mode, (b) each phase detector (PD1, PD2) in the first operating mode determines a first-mode phase difference between the clock signal (Ckin1 or CKin2) currently being used as the input clock and the output clock (CKout), and provides the first-mode phase difference for the control of the oscillator (DCO) in generating the output clock and, (c) each phase detector (PD2, PD1) in the second operating mode determines a frequency difference between the clock signal (CKin2 or Ckin1) currently not being used as the input clock and the output clock (OKout), such frequency difference being stored and continuously updated and provided as a frequency adaptation control signal (INT_OUT) for the control of the oscillator (DCO) after the switch-over to this clock signal (CKin2 or CKin1) previously not being used as the input clock, so that any frequency jump during switch-over produces, by means of the frequency adaptation control signal (INT_OUT), a substantially immediate corresponding frequency adjustment of the oscillator (DCO),
• wherein each of the at least two phase detectors (PD1, PD2) has a phase comparison device (32) comparing the phases of the clock signal (Ckin1 or CKin2) currently being used as the input clock and a first phase-shift adjusted version (CK<1:8>) of the output clock signal (CKout) to provide the first-mode phase difference determined by each phase detector (PD1, PD2) in the first operating mode, and wherein each phase detector (PD1, PD2) in the second operating mode adjusts the phase shift of a second phase-shift adjusted version (CK<1:8>) of the output clock signal (CKout)on the basis of the frequency adaptation control signal (INT_OUT).