Metastable-resistant phase comparing circuit

A phase comparing circuit for comparing phases between an external clock signal and a control clock signal, and outputting a control signal based on a result of the comparison, the phase comparing circuit comprising:

• a first storage circuit for reading the external clock signal in accordance with the control clock signal;
• a first inverter circuit for inverting a signal output from the first storage circuit based on a first threshold level;
• a second inverter circuit for inverting a signal output from the first storage circuit based on a second threshold level;
• a third inverter circuit for inverting a signal output from the first inverter circuit;
• a fourth inverter circuit for inverting a signal output from the second inverter circuit;
• a delay circuit for delaying the control clock signal by a specific time and outputting the delayed control clock signal;
• a coincidence control circuit for setting the delayed control clock signal to be active when the signals output from the third and fourth inverter circuits coincide with each other, and setting it to be inactive when the signals output from the third and fourth inverter circuits do not coincide with each other;
• and
• a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal.