Phase comparator and semiconductor device with phase comparator

A phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second edge detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit,
• wherein the status management circuit outputs a first-state signal either at a high level or at a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of the first comparison target signal when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, and when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signal changes.

A phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second edge detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit, wherein
• said first or second edge detection circuit comprises a first holding circuit for holding the first comparison target signal in timing synchronous with a clock signal, a second holding circuit for holding the second comparison target signal in timing synchronous with a clock signal and an AND circuit for carrying out logical AND between the output signal of the first holding circuit and an inverted output signal of the second holding circuit.

A phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for generating a signal corresponding to a phase difference based on a detection signal of the first edge detection circuit and a detection signal of the second edge detection circuit and outputting a state signal indicating a phase advance or delay of the first and second comparison target signals;
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit,
• wherein the status management circuit outputs a first-state signal either at a high level or a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of a first detection signal of the first edge detection circuit when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, and when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signals changes;
• and
• a phase difference signal generation circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on the signal of the state output circuit.

A semiconductor device having a phase comparator, said phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal;
• a second edge detection circuit for detecting a second comparison target signal;
• a phase difference signal generation circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit,
• wherein the status management circuit outputs a first-state signal either at a high level or at a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of the first comparison target signal when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, and when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signal changes.

A semiconductor device having a phase comparator, said phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second edge detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit,
• wherein the status management circuit outputs a first-state signal either at a high level or at a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of the first comparison target signal when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signal changes.

A semiconductor device on whose semiconductor integrated circuit substrate is formed a phase comparator, said phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second edge detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit, wherein
• when there is no phase difference between the first and second comparison target signals, said state output circuit outputs a signal for enabling the tri-state circuit to take high impedance to the control terminal of the tri-state circuit, and when there is a phase difference between the comparison target signals, said state output circuit outputs a signal for enabling current to flow for a period corresponding to a phase difference to the control terminal of the tri-state circuit, and also outputs a signal corresponding to a phase advance or delay of the first and second comparison target signals to the status management circuit.

A semiconductor device on whose semiconductor integrated circuit substrate is formed a phase comparator, said phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second edge detection circuits;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit, wherein
• said first or second edge detection circuit comprises a first holding circuit for holding the first comparison target signal in timing synchronous with the clock signal, a second holding circuit for holding the second comparison target signal in timing synchronous with the clock signal and an AND circuit for carrying out logical AND between the output signal of the first holding circuit and an inverted output signal of the second holding circuit.

A semiconductor device having a phase comparator, said phase comparator, comprising:

• a first edge detection circuit for detecting a first comparison target signal in timing synchronous with a clock signal;
• a second edge detection circuit for detecting a second comparison target signal in timing synchronous with the clock signal;
• a state output circuit for generating a signal corresponding to a phase difference based on a detection signal of the first edge detection circuit and a detection signal of the second edge detection circuit and outputting a state signal indicating a phase advance or delay of the first and second comparison target signals;
• a phase difference signal generation circuit for outputting a signal corresponding to the phase difference to a control terminal of a tri-state circuit, based on the signal of the state output circuit;
• and
• a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit,
• wherein the status management circuit outputs a first-state signal either at a high level or at a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of the first comparison target signal when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signal changes.