Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme

An apparatus comprising:

• a first power domain providing power to a plurality of first integrated circuits grouped as a first logical block, wherein the plurality of first integrated circuits includes at least one of a level shifting isolation flip flop (LSIFF) configured as a boundary device, wherein the LSIFF is operable to retain data in response to the first circuit being operable in an active power saving mode (APSM);
• and
• a second power domain providing power to a plurality of second integrated circuits grouped as a second logical block, wherein selected ones of the plurality of second integrated circuits are interfaced to the plurality of first integrated circuits by the LSIFF, wherein the LSIFF is operable to provide a configurable voltage level in the APSM, thereby providing output isolation between the first power domain and the second power domain.