Periphery clock signal distribution circuitry for structured ASIC devices
AssigneeAltera Corporation
InventorsChooi Pei Lim, Siang Poh Loh, Hong Ming Siew
Life of this patent
Estimating the term…
Abstract
A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.
Claims20
An integrated circuit device comprising:
- core circuitry having an outer periphery;
- a plurality of IO circuits disposed outside of said outer periphery, said IO circuits being grouped in a multiplicity of groups, each of which groups includes a respective subplurality of adjacent ones of said IO circuits;
- and
- clock signal routing circuitry disposed between said outer periphery and each of said groups, said routing circuitry including, in association with each of said groups, (1) a plurality of first conductors, each of which extends past all of the IO circuits in the associated group, and each of which receives a respective one of a plurality of clock signals from the core circuitry, (2) a plurality of second conductors, each of which extends across all of the first conductors to a respective one of the IO circuits in the associated group, and (3) a mask-programmable via option at each intersection between a first conductor and a second conductor.
An integrated circuit device comprising:
- core circuitry having an outer periphery;
- a plurality of IO circuits disposed outside of said outer periphery, said IO circuits being grouped in a plurality of groups, each of which includes a respective subplurality of adjacent ones of said IO circuits;
- and
- clock signal routing circuitry associated with each of said groups and disposed between the associated group and the outer periphery, the routing circuitry associated with each of said groups comprising:
- a plurality of first conductors that each extend past all of the IO circuits in the associated group and that each carry a respective one of a plurality of clock signals received from the core circuitry;
- a plurality of second conductors that each extend to a respective one of the IO circuits in the associated group and also across all of the first conductors associated with that group;
- and
- a mask-programmable via option at each intersection between a first conductor and a second conductor.
An integrated circuit device comprising:
- core circuitry including clock signal distribution circuitry;
- a plurality of IO circuits outside of the core circuitry and grouped in a plurality of groups, each of which includes a subplurality of adjacent ones of the IO circuits;
- and
- clock signal routing circuitry associated with each of the groups between the core circuitry and the associated group, the routing circuitry associated with each group comprising:
- a plurality of first conductors that each carries a respective one of a plurality of clock signals received from the clock signal distribution circuitry and that each extends past all of the IO circuits in the associated group;
- a plurality of second conductors that each connects to a respective one of the IO circuits in the associated group and that each extends across all of the first conductors associated with that group;
- and
- a mask-programmable via option at each intersection of a first conductor and a second conductor.
An integrated circuit device comprising:
- core circuitry;
- IO circuits;
- first and second intersecting conductors disposed in a portion of the device, said first conductors overlapping and connected to circuitry extending from the core circuitry into said portion, said second conductors overlapping and connected to circuitry extending from the IO circuits into said portion;
- and
- a mask-programmable connection at each intersection between the first and second conductors, whereby a signal from the core circuitry can be programmably routed to any one or more of the IO circuits.
Dependencies are inferred from the claim text.