Redundant circuit presents connections on specified I/O ports
AssigneeNVIDIA Corporation
InventorJohn M. Danskin
Life of this patent
Estimating the term…
Abstract
A method and apparatus for utilizing redundant circuitry on integrated circuits (ICs) that may increase manufacturing yields, while maintaining a predetermined set of interfaces for connection with external circuitry without drastically increasing die area and circuit complexity are provided. In this manner, even though an IC may have defects which would otherwise render it inoperable, embodiments of the present invention allow the defects to be circumscribed or avoided while still maintaining a predetermined set of interfaces, thus providing for an operational circuit. Various embodiments further provide a method for sorting or separating devices based on their level of functionality or performance, which in turn depends on their number of defects and the desired number of interfaces.
Claims11
A method of configuring an integrated circuit (IC) comprising a plurality of parallel circuit blocks, an equal number of interfaces, and selection circuitry configured to route a pathway between each of the circuit blocks and one of the interfaces, the method comprising:
- determining a number of nonfunctional circuit blocks in the plurality of parallel circuit blocks;
- if the number of nonfunctional circuit blocks is zero, controlling the selection circuitry to couple each of the plurality of parallel circuit blocks with a different one of the interfaces;
- and
- if the number of nonfunctional circuit blocks is less than or equal to a number of redundant circuit blocks in the plurality of parallel circuit blocks, controlling the selection circuitry to couple the remaining functional circuit blocks to a predetermined set of one or more interfaces no matter which circuit blocks are nonfunctional and disabling or disconnecting a clock to the nonfunctional circuit blocks.
A computing system comprising:
- one or more devices capable of external communication;
- and
- at least one integrated circuit comprising:
- a plurality of parallel circuit blocks that are parallel memory controllers;
- one or more interfaces for communicating with the devices;
- and
- a selection circuit to selectively route signals between the circuit blocks and the interfaces, wherein the selection circuit is capable of routing signals between the plurality of circuit blocks and all of the interfaces or, if any one of the circuit blocks is nonfunctional, route signals between remaining circuit blocks and a predetermined set of the interfaces.
Dependencies are inferred from the claim text.