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US 7,622,908 B2Granted
Built-in system and method for testing integrated circuit timing parameters
AssigneeMicron Technology, Inc.
InventorJongtae Kwak
Life of this patent
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AssigneeMicron Technology, Inc.
InventorJongtae Kwak
Estimating the term…
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal are generated by a test system oscillator and coupled through a clock tree of the memory device. The test system further includes a selector that sequentially selects each of the test signals applied to the data bus terminals and applies the selected test signal to a multi-phase generator. The multi-phase generator delays the selected signal by different time to generate a set of delayed signals. The phases of the delayed signals are compared to the test signal applied to the data strobe terminal to determine the delay of the compared signals relative to each other, thereby determining the timing parameter.
A system for determining the relative timing between first and second digital signals, comprising:
A method of determining the relative timing between first and second digital signals, comprising:
A system for determining the relative timing between first and second digital signals, comprising:
A system for determining the relative timing between first and second digital signals, comprising:
A method of determining the relative timing between first and second digital signals, comprising:
Dependencies are inferred from the claim text.