Stacked semiconductor packages and method therefor
AssigneeSTATS ChipPAC, Ltd.
InventorsKambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
Life of this patent
Estimating the term…
Abstract
A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first plurality of upper leads to form a stack of semiconductor packages.
Claims20
A method of stacking semiconductor packages comprising:
- providing a first semiconductor package having a first plurality of upper leads and a first wrap around a die pad;
- providing a second semiconductor package having a second plurality of lower leads and a second wrap around the die pad;
- and
- attaching the plurality of lower leads to the first plurality of upper leads and the first wrap attached to the second wrap.
A method of manufacturing a stackable semiconductor package comprising:
- providing a die pad;
- attaching a die to the die pad;
- providing a plurality of lower leads adjacent opposing sides of the die pad;
- providing a plurality of upper leads adjacent alternate opposing sides of the die pad and a widened lead tip;
- wire bonding the die to the die pad, the plurality of lower leads, and the plurality of upper leads;
- and
- encapsulating the die to expose a portion of the plurality of lower leads and a portion of the plurality of upper leads.
A stack of semiconductor packages comprising:
- a first semiconductor package having a first plurality of upper leads and a first wrap around a die pad;
- and
- a second semiconductor package having a plurality of lower leads attached to the first plurality of upper leads and a second wrap around the die pad, the second wrap attached to the first wrap.
A stackable semiconductor package comprising:
- a die pad;
- a die attached to the die pad;
- a plurality of lower leads adjacent opposing sides of the die pad;
- a plurality of upper leads adjacent alternate opposing sides of the die pad and a widened lead tip;
- wires bonding the die to the die pad, the plurality of lower leads, and the plurality of upper leads;
- and
- an encapsulant to expose a portion of the plurality of lower leads and a portion of the plurality of upper leads.
A method of manufacturing a stackable semiconductor package comprising:
- providing a die pad;
- attaching a die to the die pad;
- providing a plurality of lower leads adjacent opposing sides of the die pad;
- providing a plurality of upper leads adjacent alternate opposing sides of the die pad;
- wire bonding the die to the die pad, the plurality of lower leads, and the plurality of upper leads;
- and
- encapsulating the die to expose a portion of the plurality of lower leads and a portion of the plurality of upper leads wherein providing a plurality of upper leads provides a plated lead tip.
A stackable semiconductor package comprising:
- a die pad;
- a die attached to the die pad;
- a plurality of lower leads adjacent opposing sides of the die pad;
- a plurality of upper leads adjacent alternate opposing sides of the die pad having plated lead tips;
- wires bonding the die to the die pad, the plurality of lower leads, and the plurality of upper leads;
- and
- an encapsulant to expose a portion of the plurality of lower leads and a portion of the plurality of upper leads.
Dependencies are inferred from the claim text.