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US 7,622,779 B2Granted
Interconnection architecture and method of assessing interconnection architecture
AssigneeThe Regents of the University of California
InventorsChung-Kuan Cheng, Hongyu Chen, Bo Yao, Ronald Graham, Esther Y. Cheng, Feng Zhou
Life of this patent
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Abstract
A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected.
Claims12
A chip comprising:
- an array of hexagonal cells;
- a plurality of interconnects including a plurality of Y's, each of the Y's respectively connecting the cells in clusters of three cells each, wherein the cells within the clusters are interconnected;
- wherein the Y connecting each cluster has a node and three interconnects, each of the three interconnects having an end that connects the node to a respective one of the cells within a cluster;
- wherein each Y connects each cell of its respective cell group to the node.
1 more element
A chip comprising:
- an array of hexagonal cells;
- a plurality of interconnects including a plurality of Y's, each of the Y's respectively connecting the cells in clusters of three cells each, wherein the cells within the clusters are interconnected;
- wherein the Y connecting each cluster has a node and three interconnects connecting the node to respective ones of the cells within a cluster;
- wherein each Y connects each cell of its respective cell group to the node;
- wherein the plurality of interconnects are formed on a plurality of levels, wherein nodes of Y's connecting clusters of a lower level are interconnected by Y's of a higher level.
2 more elements
A chip comprising:
- an array of hexagonal cells;
- a plurality of interconnects including a plurality of Y's, each of the Y's respectively connecting the cells in clusters of thee cells each, wherein the cells within the clusters are interconnected;
- wherein each of the array of hexagonal cells includes a terminal for connecting to another cell;
- wherein the Y connecting each cluster includes a node and three interconnects, each of the interconnects respectively connecting the node to a separate terminal in each of the thee cells within the cluster;
- wherein each Y connects each cell of its respective cluster of thee cells to the node.
2 more elements
A chip comprising:
- an array of hexagonal cells;
- a plurality of interconnects including Y's connecting the cells in clusters of three adjacent cells each, wherein the cells in the clusters are interconnected;
- wherein the Y connecting each cluster has a node and three interconnects each of the interconnects having an end connecting the node to a respective one of the cells within a cluster;
- wherein each Y connects each cell of its respective cell group to the node.
1 more element
A chip comprising:
- an array of hexagonal cells;
- a plurality of interconnects including Y's connecting the cells in clusters of three adjacent cells each, wherein the cells in the clusters are interconnected;
- wherein the Y connecting each cluster has a node and three interconnects connecting the node to respective ones of the cells within a cluster;
- wherein each Y connects each cell of its respective cell group to the node;
- wherein the plurality of interconnects are formed on a plurality of levels, wherein nodes of Y's connecting clusters of a lower level are interconnected by Y's of a higher level.
2 more elements
Dependencies are inferred from the claim text.