Back to results
US 7,622,777 B2Granted
Semiconductor device and method for fabricating the same
AssigneePanasonic Corporation
InventorsTakashi Nakabayashi, Hideyuki Arai, Mitsuo Nissa
Life of this patent
Estimating the term…
Abstract
A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
Claims35
A semiconductor device comprising:
- a first MIS transistor formed in a first region of a semiconductor substrate;
- a second MIS transistor formed in a second region of the semiconductor substrate;
- and
- a third MIS transistor formed in a third region of the semiconductor substrate,
- wherein the first MIS transistor includes a first gate insulating film formed on the first region, a first gate electrode formed on the first gate insulating film, a first impurity doped layer formed in part of the first region located at each side of the first gate electrode and a first threshold control layer formed in part of the first region located under the first gate electrode,
- wherein the second MIS transistor includes a second gate insulating film formed on the second region, a second gate electrode formed on the second gate insulating film, a second impurity doped layer formed in part of the second region located at each side of the second gate electrode and a second threshold control layer formed in part of the second region located under the second gate electrode,
- wherein the third MIS transistor includes a third gate insulating film formed on the third region, a third gate electrode formed on the third gate insulating film, a third impurity doped layer formed in part of the third region located at each side of the third gate electrode and a third threshold control layer formed in part of the third region located under the third gate electrode,
- wherein a thickness of the second gate insulating film is substantially the same as or smaller than a thickness of the first gate insulating film and is larger than a thickness of the third gate insulating film,
- wherein the second impurity doped layer has substantially the same impurity concentration profile as an impurity concentration profile of the third impurity doped layer and has a lower impurity concentration than an impurity concentration of the first impurity doped layer, and
- wherein the second threshold control layer has substantially the same impurity concentration profile as an impurity concentration profile of the first threshold control layer and has a lower impurity concentration than an impurity concentration of the third threshold control layer.
7 more elements
Dependencies are inferred from the claim text.