US 7,622,764 B2Granted

Semiconductor device and fabricating method thereof

AssigneeDongbu Electronics Co., Ltd.

InventorJin Hyo Jung

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Abstract

Semiconductor devices and a fabricating method therefore are disclosed. One example method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode.

Claims9

Dependent claims

A semiconductor device comprising:

a gate electrode on a trench in a semiconductor substrate;
a second gate oxide layer in the trench between the gate electrode and the semiconductor substrate;
sidewall floating gates on the lower part of the lateral faces of the gate electrode;
a first gate oxide layer formed in the trench between the sidewall floating gates and a portion of the semiconductor substrate along the bottom of the trench;
a second block oxide layer between the gate electrode and the sidewall floating gates;
source and drain regions around a portion of the sidewall floating gates in the trench, wherein the source region is provided at one side of the trench and the drain region is provided along the same horizontal plane at the opposite side of the trench, and wherein the source region is elevated to the same level as the drain region;
a channel formed below a bottom of the trench;
spacers on a portion of the lateral faces of the sidewall floating gates above the trench and on the lateral faces of the gate electrode;
and
a first block oxide layer formed on lateral sides of the trench between the sidewall floating gates and the semiconductor substrate and extending along the lateral sides of the sidewall floating gates between the spacers and the sidewall floating gates.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/026,972Filed 30 Dec 2004
Priority: KR 10-2003-010110131 Dec 2003
Published: US 2005/0151185 A114 Jul 2005
Granted: 24 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/685
Programmed by hot carrier injection: from the channel
H10D 30/687
Floating-gate IGFETs: having more than two programming levels
H10D 30/6894
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having one gate at least partly in a trench