US 7,622,760 B2 · MOS type variable capacitance device

Abstract

An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode. A MOS type variable capacitance device capable of obtaining a characteristic of good linearity for a wide range relative to the inter-terminal voltage VT and capable of coping with the improvement of the performance of a VCO circuit, etc., as well as simple in the structure, and capable of being manufactured easily with no requirement for addition of masks and steps can be provided.

Claims8

Dependent claims

A MOS type variable capacitance device, comprising:

at least one first semiconductor layer constituted with a first conduction type;
at least one second semiconductor layer in adjacent to the first semiconductor layer at the surface of a semiconductor substrate and constituted with a second conduction type that is different from the first conduction type;
at least one first gate insulating layer disposed on the first semiconductor layer;
at least one second gate insulating layer disposed on the second semiconductor layer;
at least one gate layer arranged on the first gate insulating layer and the second gate insulating layer;
and
at least one first conduction type or at least one second conduction type source layer which is arranged adjacent to the first and second gate insulating layers, wherein
the impurity concentration of the first or second semiconductor layer is lower than the impurity concentration of a source layer of an identical conduction type;
when a number of the at least one gate layer is two or more, two of the gate layers are connected to each other;
when a number of the at least one first conduction type or at least one second conduction type source layer is two or more, two of the first conduction type or the second conduction type source layers are connected to each other;
and
the gate layer and the source layer are used as electrodes.

9 more elements

Dependencies are inferred from the claim text.

MOS type variable capacitance device

Life of this patent

MOS type variable capacitance device

Life of this patent

Abstract

Claims8