Test structures for electrically detecting back end of the line failures and methods of making and using the same

A method of forming a structure for testing a semiconductor topography, comprising:

• providing a primary conductive pad, a secondary conductive pad spaced laterally from the primary conductive pad, and a secondary interconnect in electrical connection with the secondary conductive pad, all of which are embedded in an insulator;
• forming a dielectric layer upon the insulator, the primary and secondary conductive pads, and the secondary interconnect;
• and
• etching a primary via through the dielectric layer down to the primary conductive pad and a secondary via through the dielectric layer down to the secondary interconnect;
• filling the primary and secondary vias with a conductive material;
• and forming an input/output connection above the primary via that is in electrical connection with both the primary via and the secondary via.